bac62a32a9
Make memory ports part of specials
...
This is needed to handle cases where a single memory has ports
in two different modules, and one of these modules is subject
to clock domain remapping. The clock domain of the port in that
module only must be remapped.
2013-05-28 16:11:34 +02:00
70ffe86356
New migen.fhdl.std to simplify imports + len->flen
2013-05-22 17:11:09 +02:00
7a74dae461
actorlib/spi: add DMAWriteController
2013-05-04 17:38:54 +02:00
c8810a016f
actorlib/spi: add DMA read controller
2013-04-30 18:55:01 +02:00
c70c71502e
actorlib/spi/SingleGenerator: use CSR alignment bits
2013-04-30 18:54:47 +02:00
fb83794ef4
actorlib/spi/Collector: cleanup, new APIs
2013-04-28 18:32:46 +02:00
692794a21f
flow: use Module and new Record APIs
2013-04-10 19:12:42 +02:00
20bdd424c8
flow: adapt to new Record API
2013-04-01 22:15:23 +02:00
c4f4143591
New CSR API
2013-03-30 17:28:41 +01:00
04df076fba
bank: automatic register naming
2013-03-12 15:45:24 +01:00
49cfba50fa
New 'specials' API
2013-02-22 17:56:35 +01:00
3fae6c8f03
Do not use super()
2012-12-18 14:54:33 +01:00
70e97e0456
Fix various errors from new bitwidth/signedness system conversion
2012-11-29 23:36:55 +01:00
fc85ca53ad
actorlib/spi: do not use MemoryPort
2012-11-26 18:27:59 +01:00
7a1a781f49
actorlib/spi: typo
2012-10-15 21:21:42 +02:00
d329d40fe9
actorlib/spi: SingleGenerator
2012-10-09 21:11:15 +02:00
c473718a12
actorlib/spi/collector: atomic update for write_count
2012-10-09 19:08:09 +02:00
24877f271b
actorlib/spi: fix memory port we/wd
2012-10-04 20:10:24 +02:00
035870703f
flow/actorlib: Simple Processor Interface (WIP)
2012-10-04 18:22:22 +02:00
Sebastien Bourdeauducq