6706b24167
software/bios/main: add missing space
2018-03-07 15:24:39 +01:00
2a50a8021a
soc/integration/soc_core: improve error message for missing csrs
2018-03-05 09:59:06 +01:00
c02b127ef9
Merge pull request #68 from mithro/improve-csr-missing-error-message
...
Improving error message when csr name is not found.
2018-03-05 08:38:25 +01:00
3e7cc2554b
Merge pull request #69 from mithro/conda-support
...
Adding conda environment and simple travis build
2018-03-04 19:50:39 +01:00
3bf5047954
travis: Adding some color.
2018-03-03 18:17:55 -08:00
083c261364
travis: Move the conda install into script so it can be folded.
2018-03-03 17:47:11 -08:00
da3189c8b5
travis: Making the output more readable.
2018-03-03 17:28:42 -08:00
12bb3ebf7c
travis: Build all the SoCs (without gateware).
...
- TODO: Build the simulator SoC.
2018-03-03 16:49:49 -08:00
e65c121adf
Adding a travis config which tests the conda environment still works.
2018-03-03 16:42:33 -08:00
795e82858f
Adding conda environment example.
...
This is a very light weight way of doing something similar to the
litex-buildenv.
2018-03-03 16:30:09 -08:00
5ef34500f7
Improving error message when csr name is not found.
...
Before;
```
"/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/integration/soc_core.py",
line 258, in get_csr_dev_address
return self.csr_map[name]
KeyError: 'core'
```
Now;
```
Traceback (most recent call last):
File "XXXX/github/enjoy-digital/litex/litex/soc/integration/soc_core.py", line 259, in get_csr_dev_address
return self.csr_map[name]
KeyError: 'ddrphy'
The above exception was the direct cause of the following exception:
Traceback (most recent call last):
...
File "XXXX/github/enjoy-digital/litex/litex/soc/interconnect/csr_bus.py", line 199, in scan
mapaddr = self.address_map(name, None)
File "XXXX/github/enjoy-digital/litex/litex/soc/integration/soc_core.py", line 269, in get_csr_dev_address
) from e
RuntimeError: Unable to find ddrphy in your SoC's csr address map.
Check BaseSoC.csr_map in XXXX/github/enjoy-digital/litex/litex/boards/targets/arty.py
Found l2_cache, timer0, ddrphy2, buttons, sdram, identifier_mem, uart, uart_phy, leds, crg in the csr_map
```
2018-03-03 16:02:44 -08:00
ab2a3277c3
Merge pull request #67 from cr1901/vivado-paths
...
xilinx/vivado: Provide a fallback mechanism for using the same root f…
2018-03-03 08:29:18 +01:00
db20df49f4
Merge pull request #65 from cr1901/tinyfpga-serial
...
platforms/tinyfpga_b: Move serial peripheral out of default I/O, make it
2018-03-03 08:28:57 +01:00
2b00b7eba4
xilinx/vivado: Provide a fallback mechanism for using the same root for Vivado and ISE toolchains.
2018-03-02 21:48:49 -05:00
fa6b256198
build/xilinx/platform: fix merge
2018-03-03 00:07:50 +01:00
87d4af0bc0
Merge pull request #66 from cr1901/arty_s7
...
boards/arty_s7: Fix IOStandard on System Clock.
2018-03-02 12:11:35 -08:00
d40c57739c
boards/arty_s7: Fix IOStandard on System Clock.
2018-03-02 13:35:43 -05:00
7bd718eb55
README: add migen installation to quick start guide
2018-03-01 10:15:43 +01:00
0332f73a7b
build/xilinx/vivado: revert toolchain_path
2018-02-28 23:45:26 +01:00
2ff50a8882
build: fix merge
2018-02-28 23:10:24 +01:00
64e4e1ce84
build: merge with migen.build 27beffe7
2018-02-28 16:49:12 +01:00
0edfd9b901
boards/kcu105: regroup sfp tx and rx
2018-02-28 14:11:58 +01:00
e71593d67e
platforms/tinyfpga_b: Move serial peripheral out of default I/O, make it
...
optional via `add_extension`.
2018-02-27 18:41:35 -05:00
c5be6e26be
README: add section for newcomers
2018-02-23 14:37:10 +01:00
f372e8c880
README: cleanup
2018-02-23 14:15:41 +01:00
fb088b79dd
README: update, migen is no longer forked
2018-02-23 14:08:13 +01:00
1925ba176f
replace litex.gen imports with migen imports
2018-02-23 13:38:19 +01:00
43164b9a2c
remove migen fork from litex
2018-02-23 13:37:26 +01:00
212e1a7076
bump to 0.2.dev
2018-02-23 13:36:32 +01:00
64aa4ae4c0
uniformize with litex cores and make things more clear about what LiteX vs Migen/MiSoC
2018-02-22 11:52:10 +01:00
aaf097056a
Merge pull request #64 from q3k/q3k/axi4lite
...
Preliminary AXI4Lite support: CSR bridge
2018-02-21 09:47:29 +01:00
688f26cc32
Change AXI interface and tidy code
...
Inspired by parts of https://github.com/peteut/migen-misc/
2018-02-21 00:00:58 +00:00
512ed2b3d6
Preliminary AXI4Lite CSR bridge support
...
This change introduces an AXI4Lite to CSR bridge. Hopefully it will
become extended in the future with full AXI support and more structures
(Wishbone bridge, interconnect, ...). For now this will do.
The bridge has been simulated (and includes an FHDL testbench) and
tested in hardware (on a Zynq 7020).
2018-02-20 21:27:51 +00:00
55fc9d2d6b
Merge pull request #60 from q3k/for-upstream/top-level-module-selection
...
Top module selection (for Verilator and Diamond)
2018-02-19 12:27:25 +01:00
7b5bd4041a
Merge pull request #57 from rohitk-singh/master
...
WIP - BIOS: Flashboot without main ram
2018-02-10 21:37:38 +01:00
c14502807e
board/targets/nexys4ddr: use MT47H64M16
2018-02-06 19:17:54 +01:00
95ebba428c
boards/platforms/nexys4ddr: add user_sw, user_btn, fix ddr3
2018-02-06 19:08:46 +01:00
ee4fa597b4
boards: add nexys4ddr
2018-02-06 14:43:20 +01:00
2ecd1b0666
Merge pull request #61 from PaulSchulz/master
...
platform/arty.py: Move Pmod definitions to 'connectors' section.
2018-01-26 01:58:37 +01:00
c83ae98be3
Merge pull request #63 from cr1901/arty_s7
...
boards/platforms: Add Arty S7 Board.
2018-01-26 01:57:50 +01:00
4607e5323f
boards/platforms: Add Arty S7 Board.
2018-01-25 18:36:32 -05:00
0ac35300c4
Merge branch 'master' of https://github.com/enjoy-digital/litex into upstream
2018-01-24 13:32:42 +10:30
4f2725809e
software/common: revert PYTHON to python3 (since breaking things)
2018-01-23 10:39:13 +01:00
4e168221d8
bios: fix riscv processor print
2018-01-23 10:33:05 +01:00
d448874879
sim: rename top module to dut and use --top-module parameter (needed for picorv32 simulation)
2018-01-23 10:28:16 +01:00
3ac28ed6f7
platform/arty.py: Move Pmod definitions to 'connectors' section.
2018-01-23 16:11:25 +10:30
ef511e7edc
Specify top-level module in Lattice Diemond build script.
...
When building multi-source files the toolchain gets confused as to which
module is top-level. This ensures that the build_name of the design is
selected.
2018-01-23 01:17:04 +00:00
ef6c517dad
Build top module as 'dut' in Verilator and set it as top-level.
...
When building a design with PicoRV32 we end up with multiple top-level
modules and Verilator becomes confused as to which is the right one.
This change ensures the dut.v generated by the sim build process has
it's top-level name set to 'dut' and that verilator is invoked with this
name.
2018-01-23 01:15:28 +00:00
a385143779
Merge pull request #59 from q3k/for-upstream/multiple-synthesis-directives
...
Allow for multiple synthesis directives in specials.
2018-01-23 01:43:23 +01:00
21bd26dcdd
Allow for multiple synthesis directives in specials.
...
This is needed to specify timing constraints on some Lattice Diamond
library specials, like the EHXPLLL.
To keep backwards compatibility we allow the directive to still be a
single string. If it's not, we assume it's an iterable.
2018-01-23 00:27:49 +00:00
Florent Kermarrec
Tim 'mithro' Ansell
William D. Jones
Sergiusz Bazanski
Paul Schulz