Commit Graph

1645 Commits

Author SHA1 Message Date
Florent Kermarrec 2079a24151 - Update README 2013-01-21 22:32:23 +01:00
Florent Kermarrec 35495d8896 - Update README 2013-01-21 22:20:44 +01:00
Sebastien Bourdeauducq a94ee3884f software/include: add float.h 2013-01-12 10:57:43 +01:00
Sebastien Bourdeauducq 83f562a76c software/include: add stdbool.h 2013-01-12 10:51:07 +01:00
Sebastien Bourdeauducq 080dbaa206 software: hide and delete .ts files 2013-01-10 18:01:42 +01:00
Sebastien Bourdeauducq 7adee988f2 software: compile compiler-rt ourselves 2013-01-10 17:59:00 +01:00
Sebastien Bourdeauducq d576893bda software/include/base/stdint.h: add INT32_C 2013-01-10 17:58:17 +01:00
Sebastien Bourdeauducq c5c29199be software: run the assembler ourselves to prevent future time wastage due to breakage of our custom Clang toolchain 2013-01-10 17:20:31 +01:00
Sebastien Bourdeauducq c490917aec software/common.mak: remove -fsigned-char from CFLAGS 2013-01-10 17:14:51 +01:00
Sebastien Bourdeauducq e4144f2c7d software/common.mak: use -target instead of deprecated -ccc-host-triple 2013-01-10 17:13:33 +01:00
Sebastien Bourdeauducq b0503aaf85 software/include/base/stdint.h: more definitions 2013-01-10 17:10:29 +01:00
Florent Kermarrec e6042c122c adapt migScope to Migen changes 2013-01-03 01:46:39 +01:00
Sebastien Bourdeauducq 51f4f920a2 Do not use super() 2012-12-18 14:55:58 +01:00
Sebastien Bourdeauducq c44ff8941c Move Token 2012-12-14 15:54:16 +01:00
Sebastien Bourdeauducq 3986790621 Remove ActorNode 2012-12-12 22:52:55 +01:00
Sebastien Bourdeauducq 053f8ed82c Fix instantiations 2012-12-06 20:57:00 +01:00
Sebastien Bourdeauducq 0392dd8ac2 bank/csrgen: interface -> bus 2012-12-06 17:15:47 +01:00
Sebastien Bourdeauducq bec02c4783 Merge branch 'master' of github.com:milkymist/milkymist-ng 2012-12-01 12:59:47 +01:00
Sebastien Bourdeauducq fee70e9866 Use Wishbone SRAM component from Migen 2012-12-01 12:59:32 +01:00
Michael Walle 7a1e4cb66b lm32: fix watchpoints
The wp_match_n vector is off by one. Which results in undefined states, at
least in simulation.

Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-30 15:22:40 +01:00
Sebastien Bourdeauducq 293a62dabe Replace Signal(bits_for(... with Signal(max=... 2012-11-29 23:41:51 +01:00
Sebastien Bourdeauducq 8bf6945dfd Use new bitwidth/signedness system 2012-11-29 23:38:04 +01:00
Sebastien Bourdeauducq 7e2bc00c0a Remove Constant 2012-11-28 23:18:53 +01:00
Sebastien Bourdeauducq 79e5f24a65 Workaround for zero-delay loop simulation problem with Icarus Verilog. TODO: clarify and revert this commit. 2012-11-28 22:49:22 +01:00
Sebastien Bourdeauducq 0620e75cb8 sram: do not use MemoryPort 2012-11-26 19:32:56 +01:00
Sebastien Bourdeauducq 0c29775a8f tb/asmicon/asmicon_wb: more complete testing by default 2012-11-26 18:19:41 +01:00
Sebastien Bourdeauducq 5ae1b2644e tb/asmicon: new initiator API 2012-11-17 19:43:30 +01:00
Michael Walle a0ff666628 lm32: replace $clog2 with macro
Unfortunately, XST does not support $clog2 with the localparam keyword
(the parameter keyword works just fine). Define a macro which replaces the
call with a constant function.

This commit can be reverted if the bug in XST is fixed.

Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-14 14:30:16 +01:00
Sebastien Bourdeauducq d15d982904 lm32: split lm32_include.v 2012-11-14 14:25:15 +01:00
Michael Walle 2ae17af75b lm32: fix documentation style
Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-14 14:09:21 +01:00
Michael Walle 4bee685c54 lm32: remove unneeded parameter in lm32_dp_ram
addr_depth can be computed by addr_width.

Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-14 14:08:41 +01:00
Michael Walle 10495e72d0 lm32: rename mem array in lm32_dp_ram
Be compatible with original proprietary DP RAM instantiation. This is
needed for simulation, where r0 is initialized to zero in lm32_cpu.v.

Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-14 14:08:06 +01:00
Michael Walle 47baad4fe1 lm32: replace clogb2 by builtin $clog2
This function is fixed in ISE since version 14.1 (see AR #44586). If the
builtin function is used, the design can be simulated with Icarus Verilog.

Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-14 14:07:28 +01:00
Sebastien Bourdeauducq ced98d7bee framebuffer: use new SingleGenerator 2012-10-09 21:11:26 +02:00
Sebastien Bourdeauducq dd6eacba62 Remove uses of the RE signal on field registers 2012-10-09 19:08:37 +02:00
Florent Kermarrec f96a28fc32 start MigLa Doc 2012-09-26 23:05:38 +02:00
Florent Kermarrec 6aeb69b329 update schematics 2012-09-18 23:09:21 +02:00
Florent Kermarrec 7b7ef4f8dc update doc 2012-09-18 16:21:32 +02:00
Florent Kermarrec 4864e08b88 add Setup.py / .gitignore
start documentation
2012-09-18 00:22:52 +02:00
Florent Kermarrec b5980a90cc add test_MigLa_1 example : csr access analyzing 2012-09-17 20:15:35 +02:00
Florent Kermarrec 0be7704a85 -add mask on Term 2012-09-17 18:37:23 +02:00
Florent Kermarrec 62bede5eef improve truthtable tool 2012-09-17 17:27:50 +02:00
Florent Kermarrec eba6a2c764 new MigLa Class, simplify & clean up 2012-09-17 17:00:47 +02:00
Florent Kermarrec dbc208395d use of new migen clock_domains convention 2012-09-17 15:27:37 +02:00
Florent Kermarrec a7658cdc6c update README 2012-09-16 11:51:03 +02:00
Florent Kermarrec d97a640b53 add ramp / square / sinus signal generation in examples 2012-09-16 11:49:16 +02:00
Florent Kermarrec 5e84b12980 simplify recorder 2012-09-16 11:48:32 +02:00
Florent Kermarrec d21099f764 examples/de1 : add ramp / square mode 2012-09-15 22:29:50 +02:00
Florent Kermarrec 88d5a593ef fix bug put_ptr on start, separate put / get processes 2012-09-15 20:22:02 +02:00
Florent Kermarrec 50da5bfbf0 remove buggy workaround on read 2012-09-15 20:13:18 +02:00