Commit Graph

7087 Commits

Author SHA1 Message Date
Gabriel Somlo 927fd675bc sdclk: additional halving to prevent clock going "too fast"
When the system/bus clock frequency is an exact power-of-2 multiple of
the desired sdcard frequency, we can drive the latter at the "maximum"
speed via the "perfect" divider. That sometimes turns out too fast, so
in order to be conservative, we double the divider, thus halving the
resulting sdclock.
2021-02-15 09:24:02 -05:00
Gabriel Somlo b03f46ffec soc: increase sdcard data/cmd timeout (from default 10e-3)
This allows the Linux driver in single-block mode (cmd17-only) to
operate solidly, without running into timeouts from LiteSDCard FSMs.

FIXME: multi-block (cmd18) transfers still time out, so revisit this
after some additional debugging.
2021-02-15 09:23:52 -05:00
enjoy-digital 07dd680a3e
Merge pull request #818 from tcal-x/vexLiteMul
Vexriscv "lite" uses "--mulDiv true", so enable "mul" instructions.
2021-02-15 15:02:47 +01:00
Florent Kermarrec 510bda4c99 cores/cpu: add initial lowRISC's Ibex support (without interrupts).
Working in simulation and on hardware: litex_sim --cpu-type=ibex, ./target.py --cpu-type=ibex.

This is currently doing a git clone of ibex and opentitan repositories but we'll
create a pythondata-cpu-ibex package in the future.

litex_sim --cpu-type=ibex:

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2020 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Feb 15 2021 11:57:50
 BIOS CRC passed (e7517f7b)

 Migen git sha1: 7014bdc
 LiteX git sha1: ead12df2

--=============== SoC ==================--
CPU:		Ibex @ 1MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		32KiB
SRAM:		8KiB
MAIN-RAM:	262144KiB

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--
2021-02-15 12:02:25 +01:00
Tim Callahan 5cb467cae3 Vexriscv "lite" uses "--mulDiv true", so enable "mul" instructions.
Signed-off-by: Tim Callahan <tcal@google.com>
2021-02-14 14:16:14 -08:00
Florent Kermarrec ead12df21b soc/cores/gpio: review/simplify #810.
Use irqs dict and "rise", "fall" strings instead of Enums:

Ex: pads=Signal(8), irqs={}                    : 8-bit Input, No IRQ.
    pads=Signal(8), irqs={0: "rise", 7: "fall"}: 8-bit Input, rising IRQ on 0, falling IRQ on 1.

Also simplify the logic.
2021-02-12 16:21:01 +01:00
enjoy-digital 89454d2df3
Merge pull request #810 from antmicro/gpio_interrupts
Add support for interrupts on GPIOIn
2021-02-12 15:51:25 +01:00
enjoy-digital 159155b3e6
Merge pull request #816 from geertu/software-demo-Drop-bogus-the-in-README
software/demo: Drop bogus "the" in README
2021-02-12 15:32:50 +01:00
Geert Uytterhoeven d91262e85c software/demo: Drop bogus "the" in README
Fixes: e7e28f2438 ("Change wording of demo README")
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-02-12 15:15:55 +01:00
enjoy-digital 0366a03c87
Merge pull request #813 from antmicro/jboc/lpddr4
software/bios: add option to disable BIOS prompt
2021-02-12 14:08:34 +01:00
enjoy-digital 25244629e9
Merge pull request #815 from nickoe/reword_demo_readme
Change wording of demo README
2021-02-12 13:57:19 +01:00
Florent Kermarrec 3b00a7c4fe README: Add link to the Wiki in the Welcome section. 2021-02-12 13:40:11 +01:00
Nick Østergaard e7e28f2438 Change wording of demo README
Change wording of demo README to make it more clear what the process is
and how things related.  This should help the newcomer and it still
usefull for the triained.

Change the command example to be more copy paste friendly.

Fixes #814
2021-02-11 21:35:02 +01:00
Jędrzej Boczar 5f1edccd2e software/bios: add option to disable BIOS prompt 2021-02-11 10:49:45 +01:00
Florent Kermarrec 041aa9bf6f soc/cores/clock/xilinx_us/USIDELAYCTRL: make sure sys clock domain is reseted when reference clock domain is reseted. 2021-02-09 19:06:49 +01:00
Florent Kermarrec 126dd267d6 soc/interconnect/axi/AXIInterface: add optional tkeep. 2021-02-09 16:27:48 +01:00
Robert Szczepanski 15b3d932a4 gpio: add support for interrupts on GPIOIn 2021-02-09 15:29:31 +01:00
enjoy-digital 018094abb2
Merge pull request #809 from stffrdhrn/mor1kx-smp
cpu/mor1kx: Add initial SMP support to cpu core
2021-02-09 09:54:49 +01:00
enjoy-digital 95b310ee0f
Merge pull request #807 from antmicro/revert-bitstream-device-changes
build/xilinx/symbiflow: fix bitstream_device select
2021-02-09 09:26:48 +01:00
enjoy-digital b9bc1d8457
Merge pull request #806 from geertu/bios-improvements
Bios improvements
2021-02-09 09:24:35 +01:00
Stafford Horne 2f2b047f2e cpu/mor1kx: Add initial SMP support to cpu core
In order for mor1kx to run an SMP kernel shadow registers must be
enabled.  This patch adds two new variants:

 - linux+smp - basic linux + smp support
 - linux+smp+fpu - linux with FPU and smp support
2021-02-09 07:06:07 +09:00
Jan Kowalewski ad760d491c build/xilinx/symbiflow: fix bitstream_device select
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
2021-02-08 15:38:30 +01:00
Geert Uytterhoeven 84e5130ac5 software/bios/console: Call putsnonl() from puts()
puts() and putsnonl() are very similar, and can share code.
Reduce code size by making the former call the latter.

Impact for a RISC-V build:

    $ size console.o.orig console.o
       text	   data	    bss	    dec	    hex	filename
	868	      0	     12	    880	    370	console.o.orig
	832	      0	     12	    844	    34c	console.o

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-02-08 14:05:31 +01:00
Geert Uytterhoeven 8e4202ced1 software/bios/readline: Fix warnings if char is signed
When building with --cpu-type=mor1kx:

    litex/soc/software/bios/readline.c: In function 'readline':
    litex/soc/software/bios/readline.c:271:3: warning: case label value exceeds maximum value for type [-Wswitch-outside-range]
      271 |   case KEY_END:
	  |   ^~~~
    litex/soc/software/bios/readline.c:297:3: warning: case label value exceeds maximum value for type [-Wswitch-outside-range]
      297 |   case KEY_DEL:
	  |   ^~~~
    litex/soc/software/bios/readline.c:281:3: warning: case label value exceeds maximum value for type [-Wswitch-outside-range]
      281 |   case DEL:
	  |   ^~~~

The C standard does not specify the signedness of "char", hence this
depends on the implementation.  On e.g. RISC-V, "char" is unsigned, but
on OpenRISC, it is signed.

Fix this by making the "ichar" variable explicitly unsigned.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-02-08 14:05:31 +01:00
Florent Kermarrec 5430c1455e software/demo: add support for absolute/relative --build-path and simplify comment. 2021-02-08 10:29:26 +01:00
enjoy-digital 876ee69e69
Merge pull request #803 from hansfbaier/master
demo: more helpful usage message / support Altera JTAG in litex_term
2021-02-08 10:18:58 +01:00
Florent Kermarrec b485829ec4 MANIFEST.in: update. 2021-02-08 10:11:10 +01:00
Hans Baier 7dae0aa09b litex_term: support Intel/Altera nios2-terminal 2021-02-08 11:42:37 +07:00
Hans Baier 6f63fc104e demo: more helpful usage message 2021-02-06 07:15:12 +07:00
Florent Kermarrec 5cb9f487a2 tools/litex_server: remove JTAGUART's binary_mode parameter (we are now only supporting binary_mode). 2021-02-05 12:38:20 +01:00
Florent Kermarrec 468b916a4f tools/litex_term: add --jtag-config parameter to select OpenOCD JTAG configuration file. 2021-02-05 09:43:32 +01:00
Florent Kermarrec 4f15be746c tools/litex_term: always use binary mode (for jtag_uart and jtagbone) and remove parameter.
Fix jtag_uart regression and allow serialboot.
2021-02-05 09:40:21 +01:00
enjoy-digital 92f4cd1423
Merge pull request #799 from antmicro/add_xc7a200t_to_symbiflow
build/xilinx: add xc7a200t-sbg484-1 to symbiflow toolchain
2021-02-04 16:41:45 +01:00
enjoy-digital 0006efe6ea
Merge pull request #800 from geertu/doc-sphinx-v1-fix
doc: Fix doc build with Sphinx v1.x
2021-02-04 12:24:49 +01:00
Florent Kermarrec 4d1deffbb0 jtagbone/openocd: add binary mode on JTAGUART to fix "\n" to "\r" remapping that is not wanted in binary mode. 2021-02-04 11:44:43 +01:00
Geert Uytterhoeven af13f43e60 doc: Fix doc build with Sphinx v1.x
When building the linux-on-litex-vexriscv documentation with Sphinx
v1.8.5:

    Sphinx error:
    master file linux-on-litex-vexriscv/build/orangecrab/doc/contents.rst not found

The default value of "master_doc" was changed from "contents" to "index"
in Sphinx v2[1].  As the LiteX doc system creates "index.rst", it thus
fails to build with Sphinx v1.x.

Explicitly configure "master_doc" to "index", to make it work with all
versions of Sphinx, regardless of the default.

[1] https://www.sphinx-doc.org/ca/latest/usage/configuration.html?highlight=master_doc

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-02-04 09:40:04 +01:00
Jan Kowalewski 57915db746 build/xilinx: add xc7a200t-sbg484-1 to symbiflow toolchain
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
2021-02-03 15:18:48 +01:00
enjoy-digital b589959084
Merge pull request #796 from antmicro/jboc/gtkwave-savefiles
Fix gtkwave.py to be compatible with python 3.6
2021-02-02 16:30:01 +01:00
Jędrzej Boczar b1fb141d1f Fix gtkwave.py to be compatible with python 3.6 2021-02-02 11:14:16 +01:00
Florent Kermarrec ba7c503fb6 tools/litex_sim: move gtkw import to generate_gtkw_savefile.
This fixes litex_sim use with python 3.6 and raise an error when --gtkwave-savefile
is used with python 3.6.
2021-02-02 10:13:23 +01:00
enjoy-digital 659751d202
Merge pull request #795 from antmicro/jboc/gtkwave-savefiles
Add automatic generator of GTKWave savefiles
2021-02-02 09:59:18 +01:00
enjoy-digital 2f907d6e1e
Merge pull request #790 from antmicro/jboc/8phases
software/liblitedram: support PHYs with more than 4 DFI phases
2021-02-02 09:43:17 +01:00
enjoy-digital d76e0dcede
Merge pull request #791 from antmicro/jboc/init-mr
software/liblitedram: selectable write leveling MR (for LPDDR4 support)
2021-02-02 09:36:31 +01:00
enjoy-digital 4c1dbf9991
Merge pull request #794 from geertu/vexriscv-sbt-failures-are-fatal
cpu/vexriscv_smp: Make sbt failures fatal
2021-02-01 15:16:06 +01:00
Geert Uytterhoeven 7b3737f531 cpu/vexriscv_smp: Make sbt failures fatal
When using a non-default VexRiscv cluster config, the netlist for that
config needs to be generated.  This requires sbt to be installed.
If sbt is missing, an error message is printed:

    sh: 1: sbt: not found

This message may easily be lost in the noise, as the build continues, and fails
later with:

    ERROR: Can't open input file `litex/pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_Ood_Wm.v' for reading: No such file or directory

Make the root cause more visible by raising an OSError, and aborting the
build.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-02-01 13:54:59 +01:00
Jędrzej Boczar fc9ef4c255 litex_sim: add --gtkwave-savefile argument with example signals 2021-02-01 13:22:30 +01:00
Jędrzej Boczar 01b900f4e0 Add GTKWave savefile generator 2021-02-01 13:22:30 +01:00
Florent Kermarrec 8623536a8a build/generic_platform: avoid removing X pins from named_sc.
We need them on Gowin FPGAs with embedded SDRAM where SDRAM pins are not real IOs.
2021-02-01 13:12:25 +01:00
Florent Kermarrec f324f9531a build/gowin: Don't generate IO_LOC is pin name is X. 2021-02-01 13:08:37 +01:00
enjoy-digital fd33e360fb
Merge pull request #792 from euryecetelecom/master
Add flash method to openFPGALoader class
2021-01-30 21:35:09 +01:00