96527b5a3a
soc/interconnect/stream/gearbox: remove bit reversing by changing words order
2018-11-30 23:12:30 +01:00
1c8c2426b9
Merge branch 'master' of http://github.com/enjoy-digital/litex
2018-11-27 17:45:07 +01:00
8887fc24c4
build/xilinx/vivado: disable xpm by default (can be enabled by passing enable_xpm=True to build).
...
Old version of Vivado don't have XPM support and enable it break the build.
Enabling XPM is only useful in some cases, we can do it manually.
2018-11-27 17:42:39 +01:00
cc4ba65659
Merge pull request #130 from jfng/master
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litex_sim: add --trace argument
2018-11-27 17:35:03 +01:00
ec46beeb47
targets/ulx3s, versa_ecp5: use ECP5PLL
2018-11-27 17:31:53 +01:00
71398e0155
litex_sim: add --trace argument
2018-11-27 17:26:32 +01:00
18048eb454
cores/clock: test and fix ECP5PLL, phase still not implemented.
2018-11-27 17:24:22 +01:00
20dd95c541
boards/platforms/ulx3s: add gpios 0-3
2018-11-27 14:15:35 +01:00
909cff1940
bios/sdram: flush l2 cache only when present
2018-11-26 18:37:45 +01:00
2ad83778bf
bios: allow testing main_ram at init when using an external controller
2018-11-26 15:21:00 +01:00
cdfe0454bb
build/microsemi/libero_soc: small cleanup
2018-11-26 11:35:06 +01:00
4592e3235b
Merge pull request #128 from mithro/small-fix
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Two small fixes
2018-11-26 09:48:10 +01:00
4f565c5179
stream.Endpoint: Pass extra arguments to superclass.
2018-11-25 12:57:11 -08:00
3b9e4c4df6
wishbone.SRAM: Support non-32bit wishbone widths.
2018-11-25 12:56:37 -08:00
515c06219a
cores/clock: add ECP5PLL
2018-11-24 00:47:38 +01:00
7623b5dd96
soc/interconnect/stream/gearbox: inverse bit order
2018-11-23 18:34:24 +01:00
d32e393033
soc/cores/spi_flash: add missing endianness parameter
2018-11-23 18:33:53 +01:00
c954943e02
platforms/avalanche: add IOStandard on ddram pins
2018-11-23 12:47:45 +01:00
09a1cda943
build/microsemi/libero_soc: associate timings constraints with synthesis/place&route/timing verification
2018-11-23 09:30:13 +01:00
a98e1ad689
build/microsemi/libero_soc: add additional_timing_constraints
2018-11-23 09:04:42 +01:00
b166882308
build/microsemi/libero_soc: use die/package/speed from platform.device and add tcl_name helper
2018-11-23 08:26:31 +01:00
9df75d7d63
platforms/avalanche: add package/speed to platform.device
2018-11-23 08:24:29 +01:00
953b1f70df
build/microsemi/libero_soc: remove previous impl directory if exists
2018-11-23 08:11:57 +01:00
18d513a146
build/microsemi/libero_soc: give better names to pdc files: io/fp
2018-11-23 08:03:55 +01:00
4f092dbe35
build/microsemi/libero_soc: add additional_constraints
2018-11-22 18:40:19 +01:00
206c9a4697
platforms/avalanche: fix ddram dq7
2018-11-22 18:13:33 +01:00
f003407776
build/microsemi/libero_soc: add {} around port name.
2018-11-22 17:37:03 +01:00
beeca856e5
utils/litex_read_verilog: fix generated indent on instance
2018-11-22 17:33:46 +01:00
1fe7d09fb5
soc/integration/soc_core: add csr_map_update function
2018-11-21 08:39:52 +01:00
ab799f7bd7
Merge pull request #127 from cr1901/picorv32-data
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libbase/crt0-picorv32: Add support for .data sections.
2018-11-20 21:15:50 -08:00
89c702187a
libbase/crt0-picorv32: Add support for .data sections.
2018-11-21 00:13:13 -05:00
80bdae0e55
build/sim/verilator: add trace parameter to enable tracer
2018-11-20 18:54:22 +01:00
7359a99bf9
soc_core: convert cpu_type="None" string to None
2018-11-20 17:45:11 +01:00
5805d63013
build/microsemi/libero_soc: only associate timings constraint to timing check (otherwise we loose io constraints...), use default settings for place & route
2018-11-19 16:36:30 +01:00
85f7666207
build/microsemi/common: add async reset synchronizer (using DFN1P0)
2018-11-19 15:35:59 +01:00
e3c6bd5846
build/microsemi/libero_soc: pass timing constraints to synthesis, place & route and timing verification tools
2018-11-19 12:50:07 +01:00
4c966114f8
build/microsemi/libero_soc: add timing constraints support
2018-11-19 09:40:16 +01:00
60faae490a
boards/platforms/avalanche: fix swapped serial pins
2018-11-19 08:45:55 +01:00
52396add5d
boards/platforms/avalanche: rename rst to rst_n (active low reset)
2018-11-19 08:14:46 +01:00
8e07e1a099
build/microsemi/libero_soc: associate .pdc to place and route tool.
...
For constraint to be applied, we also to associate them with the tool that will use it.
2018-11-19 08:07:36 +01:00
5137c2bf88
test/test_targets: update
2018-11-17 17:36:57 +01:00
a5ed42ec68
soc/interconnect/stream: add Gearbox
2018-11-17 17:29:45 +01:00
11d536dc4d
test: remove test_bitslip (integrated in migen)
2018-11-17 17:29:09 +01:00
a25645afa6
utils: add litex_read_verilog utility
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generate Migen's modules from verilog files
2018-11-16 16:09:44 +01:00
a538d36268
create utils directory and move the litex utils to it
2018-11-16 14:37:19 +01:00
45ec78e93a
build/microsemi/libero_soc: able to generate design script (tcl) and design constraint (pdc) for libero soc / avalanche board.
2018-11-16 12:19:03 +01:00
4cb6583b4e
build: add microsemi template for polarfire fpgas support
2018-11-15 18:21:41 +01:00
bc173380f2
Merge pull request #126 from mithro/toolchain-fix
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lattice/icestorm: Add toolchain_path so it doesn't end up kwargs.
2018-11-13 16:20:57 -08:00
b1425ba85f
lattice/icestorm: Add toolchain_path so it doesn't end up kwargs.
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Fixes the following error;
```
make[1]: Leaving directory `/home/travis/build/mithro/litex-buildenv/build/ice40_hx8k_b_evn_base_lm32.lite/software/stub'
Traceback (most recent call last):
File "./make.py", line 164, in <module>
main()
File "./make.py", line 148, in main
vns = builder.build(**dict(args.build_option))
File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/soc/integration/builder.py", line 171, in build
toolchain_path=toolchain_path, **kwargs)
File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/soc/integration/soc_core.py", line 389, in build
return self.platform.build(self, *args, **kwargs)
File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/build/lattice/platform.py", line 29, in build
return self.toolchain.build(self, *args, **kwargs)
File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/build/lattice/icestorm.py", line 139, in build
v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/build/lattice/platform.py", line 26, in get_verilog
**kwargs)
File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/build/generic_platform.py", line 368, in get_verilog
create_clock_domains=False, **kwargs)
TypeError: convert() got an unexpected keyword argument 'toolchain_path'
```
2018-11-13 16:18:08 -08:00
af25bf2bc0
soc_core: check for cpu before checking interrupt
2018-11-13 16:17:49 +01:00
Florent Kermarrec
Jean-François Nguyen
Tim 'mithro' Ansell
William D. Jones