7 commits

Author	SHA1	Message	Date
Florent Kermarrec	f65c0a3c95	adapt LiteScope to new SoC	2015-04-01 22:46:24 +02:00
Florent Kermarrec	a874f85854	litescope: use CRG from Migen	2015-03-17 11:52:54 +01:00
Florent Kermarrec	649cdeb265	liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen	2015-03-01 16:48:41 +01:00
Florent Kermarrec	b32a0e6f9e	liteeth: create example design derived from SoC that can be used on all targets with Ethernet pins	2015-02-28 23:33:00 +01:00
Florent Kermarrec	5c43d4d091	litescope: create example design derived from SoC that can be used on all targets	2015-02-28 22:19:24 +01:00
Florent Kermarrec	69e869893d	remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)	2015-02-28 11:36:15 +01:00
Florent Kermarrec	df0ba1b03c	litescope: create example_designs directory	2015-02-28 10:42:12 +01:00

Renamed from misoclib/tools/litescope/targets/simple.py (Browse further)