0f8f89a269
update clock constraints for SATA1 and use sys_clk of 200MHz
...
- data seems stable (mila capture) except when receive the ALIGN primtive from the device, we should maybe disable alignment on the HOST when link is ready...
2014-12-17 19:24:23 +01:00
5a16a5b46d
add very basic PHY stimulator (to see HDD behaviour when we send primitives)
2014-12-17 17:57:37 +01:00
2c0115262b
fix compilation and use new cpu_csr_regions
2014-12-17 12:03:52 +01:00
8f9efde39e
regroup all constants/ definitions in common
2014-12-14 10:45:26 +01:00
64ed34b35a
clean up
2014-11-11 16:15:28 +01:00
47b5ff5e33
move code and create a directory for each layer
2014-11-03 17:38:12 +01:00
3f7406a937
various fixes and simplifications, SATA1 & SATA2 OK
2014-10-28 02:15:19 +01:00
e2cbb3a048
platforms: merge but keep support for iMPACT for now (xc3sprog need to be tested on Windows)
2014-10-24 12:32:08 +02:00
b284819d18
revert simulation design and add wave
2014-09-30 11:10:15 +02:00
110580eb2e
add .payload. to Sink and Source to be compatible with upstream Migen
2014-09-30 11:03:36 +02:00
f5001751d0
instanciate GTXE2_COMMON (seems recommended in AR43339)
2014-09-30 10:57:52 +02:00
cf084fd079
test to visualize OOB with Miscope
2014-09-30 10:17:15 +02:00
0791b9e2e4
sim working
2014-09-29 17:12:02 +02:00
c27f24c4c0
reorganize code
...
- use sys_clk of 166.66MHz and using it instead of sata clk.
- rename clocking to CRG since it also handles resets.
- create datapath and move code from gtx.
2014-09-27 15:34:28 +02:00
879478a6e4
clocking: clean up and add comments
2014-09-27 13:33:43 +02:00
1d053bd7ee
modify TestDesign to be able to simulate phy with host <--> device loopback
2014-09-25 15:37:49 +02:00
435bc22fa0
integrate phy in test design and start fix syntax errors
2014-09-24 16:07:34 +02:00
7e31ef2152
init with repo with simple TestDesign
2014-09-22 13:36:43 +02:00
Florent Kermarrec