uint32_t is treated as `unsigned int` by the 64-bit compiler, and
as `long unsigned int` by the 32-bit compiler. As such, we'll get
a warning on one or the other regardless of whether we use "%ld"
or "%d" with printf:
on 64-bit (rocket, using "%ld"):
./litex/litex/soc/software/liblitesata/sata.c: In function 'sata_init':
./litex/litex/soc/software/liblitesata/sata.c:87:45:
warning: format '%ld' expects argument of type 'long int', but
argument 2 has type 'uint32_t' {aka 'unsigned int'} [-Wformat=]
87 | printf("Capacity: %ldGB\n", capacity);
| ~~^ ~~~~~~~~
| | |
| | uint32_t {aka unsigned int}
| long int
| %d
on 32-bit (vexriscv, using "%d"):
./litex/litex/soc/software/liblitesata/sata.c: In function 'sata_init':
./litex/litex/soc/software/liblitesata/sata.c:87:44:
warning: format '%d' expects argument of type 'int', but
argument 2 has type 'uint32_t' {aka 'long unsigned int'} [-Wformat=]
87 | printf("Capacity: %dGB\n", capacity);
| ~^ ~~~~~~~~
| | |
| int uint32_t {aka long unsigned int}
| %ld
This patch changes `capacity` to `unsigned`, which has the same size
as `uint32_t`, but has the advantage of being treated the same by
`printf` regardless of whether we use the 32- or 64-bit compiler.
Changes in Zephyr require updated script to generate correct overlay.
This commit splits CSR regions that were being added to overlay as
single register into separate registers with names.
It also prints their size in bytes instead of used subregisters.
I also added LITEX_CSR_DATA_WIDTH to generated config parameters.
To limit code duplication, I added functions used for indenting text.
Additionally, I updated formatting functions to take list of registers
and then format it, instead of just surrounding already formatted text
with braces.
- Cosmetic changes and increase similarities with other CPUs.
- Simplification.
- Allow converting AXI to Wishbone or AXI-Lite (Still keep wishbone as default).
- Connect reset from SoC.
- Reorder AXI signals by channels.
- Move JTAG integration to add_jtag method.
OpenFPGA build backend was an experimental build backend for OpenFPGA/SOFA chips.
OpenFPGA is now providing a new FOEDAG build framework abstracting things and providing
a regular .tcl/.sdc based toolchain.
- Detect activation from passed pads: If p and n present -> Activate.
- Make code a bit more generic to avoid if/else.
- Keep change self contained to VideoHDMIPHY to avoid propagating features to VideoHDMI10to1Serializer.
(Less optimal in term of resources since doubling the serializers, but should be negligible and we are
fixing a hardware issue here...).
enjoy-digital
Icenowy Zheng
Gabriel Somlo
Tim 'mithro' Ansell
Michal Sieron
Jevin Sweval
Tony McDowell
Massimiliano Giacometti
Eric Matthews