Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
4,039 Commits 40 Branches 14 Tags 51 MiB
Commit Graph

4039 Commits

Author SHA1 Message Date
Florent Kermarrec af25bf2bc0 soc_core: check for cpu before checking interrupt 2018-11-13 16:17:49 +01:00
Florent Kermarrec b4bdf2a023 cores/clock/S7: just reset the generated clock, not the PLL/MMCM 2018-11-13 14:47:04 +01:00
Florent Kermarrec 86fd945bc3 bios/main: fix typo on mor1kx 2018-11-13 11:16:06 +01:00
Florent Kermarrec af95028574 cpu/mor1kx: use clang only for linux variant 2018-11-13 11:09:39 +01:00
Florent Kermarrec 04523bc28a xilinx/vivado: fix migen merge 2018-11-12 16:31:51 +01:00
Florent Kermarrec f3343c46fc platforms: remove versaecp55g_sdram 2018-11-12 12:45:33 +01:00
Florent Kermarrec 58414b1819 build/xilinx/vivado: merge migen change 2018-11-12 12:00:30 +01:00
Florent Kermarrec a7f17f9915 build: use default toolchain_path on all backend when passed value is None 2018-11-12 11:48:30 +01:00
Florent Kermarrec eed1d5cb2e generic_platform: use set for sources 2018-11-12 11:47:39 +01:00
Florent Kermarrec 665fff8390 build: merge more migen changes 2018-11-12 11:26:35 +01:00
Florent Kermarrec 70f48775de platforms/versa_ecp5: import migen changes 2018-11-12 10:52:28 +01:00
Florent Kermarrec 4ff241b981 targets/ulx3s,versa_ecp5: prjtrellis toolchain renamed to trellis 2018-11-12 10:47:33 +01:00
Florent Kermarrec cb86728ad1 build/lattice: import changes from migen 2018-11-12 10:46:49 +01:00
Florent Kermarrec 8574c62f75 targets/versa_ecp5: increase sys_clk_freq to 50MHz 2018-11-12 10:12:10 +01:00
Florent Kermarrec a752dafb14 targets: add versa_ecp5 with sdram (ecp5 soc hat) at 25MHz/no pll 2018-11-12 09:45:59 +01:00
Florent Kermarrec 87c7d23d16 targets/ulx3s: for now revert to 25MHz clock/no pll 2018-11-12 09:44:32 +01:00
Florent Kermarrec d1baae36a6 platforms/versa_ecp5: add ecp5 soc hat ios 2018-11-12 09:43:31 +01:00
Florent Kermarrec b3bf1c9517 Merge branch 'master' of http://github.com/enjoy-digital/litex 2018-11-12 08:12:07 +01:00
enjoy-digital 1be6762dfe
Merge pull request #125 from daveshah1/trellis_sdram 
ecp5 soc hat wip
 2018-11-12 08:11:57 +01:00
Florent Kermarrec 425ad755ec plarforms: rename versa/versaecp55g to versa_ecp3/versa_ecp5 2018-11-12 08:06:22 +01:00
Florent Kermarrec c57aa545ca targets/ulx3s: get memtest working by disabling sdram refresh 
Will need to be fixed...
 2018-11-09 18:40:14 +01:00
Florent Kermarrec 9a6447172a soc/integration/soc_sdram: allow using axi interface with litedram 2018-11-09 15:42:34 +01:00
Florent Kermarrec 416bdb6483 boards/platforms: add avalanche polarfire board ios definition 2018-11-08 18:24:12 +01:00
David Shah f08f80bed1 working on Versa-5G dram 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-06 14:39:25 +00:00
Florent Kermarrec fc0d5c3963 bios/sdram: iterate multiple time for write leveling and add vote to eliminate transcients 2018-11-05 18:44:28 +01:00
Florent Kermarrec 09f962fdc4 target/kcu105: add reset button 2018-11-05 18:41:49 +01:00
Florent Kermarrec 169f8d8cb5 boards/platforms/kcu105: fix sdram/dq pin swap 2018-11-05 17:01:42 +01:00
David Shah d78d5d3e7f Debugging ULX3S SDRAM 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-05 11:54:22 +00:00
Florent Kermarrec 2624ba48c2 bios/sdram: replace DDR3_MR1 constant with DDRX_MR1 2018-11-05 10:47:25 +01:00
Florent Kermarrec 6be74aa17f boards/targets: add kcu105 2018-11-05 10:44:50 +01:00
enjoy-digital 93c623251b
Merge pull request #122 from daveshah1/trellis_ulx3s 
Switch Trellis build to use LPF constraints; working on ULX3S
 2018-11-02 19:59:23 +01:00
enjoy-digital 00ef8240ef
Merge pull request #124 from jfng/master 
build/sim/verilator: don't use --threads when $(THREADS) is unset
 2018-11-02 17:46:04 +01:00
Jean-François Nguyen dcbe759b64 build/sim/verilator: don't use --threads when $(THREADS) is unset 2018-11-02 14:22:44 +01:00
Florent Kermarrec 6f38213acc boards/platforms/kc705: add user_sma_mgt_refclk 2018-11-01 10:52:01 +01:00
enjoy-digital 4cdd679908
Merge pull request #123 from cr1901/prv32-min 
PicoRV32 Enhancements
 2018-11-01 10:45:32 +01:00
William D. Jones e56f71824d libbase/crt0-picorv32: Emulate support for a relocatable IRQ vector (hardcoded at synthesis time). 2018-11-01 05:02:04 -04:00
William D. Jones f32121e0e1 cpu/picorv32: IRQ vector needs to be moved to 16 bytes after the RESET vector. 2018-11-01 02:23:01 -04:00
William D. Jones 77389d27b5 libbase/crt0-picorv32: Ensure BSS is cleared on boot. 2018-11-01 02:18:03 -04:00
Florent Kermarrec f7969b660a cores/clock: add with_reset parameter (default to True) 
In some cases we want to generate the reset externally.
 2018-10-31 16:23:23 +01:00
David Shah 0729b3a059 ulx3s: Connect SDRAM clock 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-31 13:29:35 +00:00
David Shah 8404434956 Fix Trellis build; ULX3S demo boots to BIOS 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-31 12:27:05 +00:00
David Shah 0c1d8d5993 trellis: Switch to using LPF for constraints 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-31 11:43:39 +00:00
Florent Kermarrec 445c49400f boards/platforms/kcu105: add sfp_tx/rx definition 2018-10-31 10:48:48 +01:00
William D. Jones f69bd877b9 cpu/picorv32: Create minimal variant (disable mul/div insns, most speed optimizations). 2018-10-30 06:00:45 -04:00
William D. Jones d05fe673a0 cpu/picorv32: Extract picorv32 parameters from Instance constructor to facilitate creating variant CPUs. 2018-10-30 06:00:45 -04:00
Florent Kermarrec e9d4c882ba build/lattice/prjtrellis: fix default toolchain_path 2018-10-30 10:28:12 +01:00
Florent Kermarrec 468780c045 soc/cores/spi_flash: add endianness parameter 2018-10-30 10:19:21 +01:00
Florent Kermarrec 6f3131e259 soc/interconnect/stream_packet: use reverse_bytes from litex.gen 2018-10-30 10:16:55 +01:00
Florent Kermarrec b796853893 gen: add common with reverse_bits/reverse_bytes functions 2018-10-30 10:15:29 +01:00
Florent Kermarrec 71fc34d7b6 boards/targets/ulx3s: reduce l2_size 2018-10-30 10:14:48 +01:00