b033d91738
Merge pull request #1294 from suppamax/cva6
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add cva6 cpu
2022-05-24 19:28:57 +02:00
a67cd6e442
build/osfpga: Add include_path support.
2022-05-24 17:33:03 +02:00
3bf5c11928
build/osfpga: Add test_soc.py to test simple SoC builds.
2022-05-24 17:33:00 +02:00
5140668c31
build/osfpga: Rename blinky.py to test_blinky.py.
2022-05-24 17:32:54 +02:00
5bdc0cbc63
build/osfpga: Add macros dict and use it for now to derivate macro from device.
2022-05-24 17:32:49 +02:00
c2e9125d05
Merge pull request #1309 from jevinskie/jev/bug/intel-clocking-indent
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Intel Clocking: compute_config() fix indent causing PLL config error
2022-05-24 09:31:54 +02:00
68fe6a30fd
Intel Clocking: compute_config() fix indent causing PLL config error
2022-05-23 12:12:32 -07:00
6e42082128
Merge pull request #1307 from jevinskie/jev/feat/altera_reset_pretty_names
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AlteraAsyncResetSynchronizer: prettify instance names
2022-05-23 10:00:16 +02:00
90840ff953
Merge pull request #1305 from jevinskie/jev/feat/platform_request_remaining
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Add request_remaining("name") that returns unallocated pins.
2022-05-23 09:57:29 +02:00
b510157b2f
Merge pull request #1304 from jevinskie/jev/bug/quartus-error-bailout
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Quartus build: bail out on error
2022-05-23 09:56:32 +02:00
7d1c9a9001
AlteraAsyncResetSynchronizer: prettify instance names
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This makes debugging e.g. conflicting drivers easier since the errors will display the clock domain name.
2022-05-21 16:22:41 -07:00
0b9ffb6adb
Add request_remaining("name") that returns unallocated pins.
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Improve error reporting on request_all().
2022-05-21 16:03:56 -07:00
9f7028e088
Quartus build: bail out on error
2022-05-21 16:02:25 -07:00
a426ec9e2f
cpu/vexriscv_smp/core: Only use Linux variant (Since similar to standard).
2022-05-20 18:52:46 +02:00
9ee9eb16a4
Merge pull request #1302 from tonymcdowell-rs/master
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litex_setup: fix path reference for python3 binary on non-Linux hosts
2022-05-20 12:12:27 +02:00
2e9b0331db
litex_setup: fix path reference for python3 binary on non-Linux hosts
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the python binary is stored in the "Program Files" directory. without
delimiting the path the calls to the binary will fail on Windows hosts.
2022-05-19 12:50:50 -06:00
c95ddbbff8
UART_POLLING
2022-05-19 15:07:46 +02:00
1d20bbcd01
software/liblitesata/sata_init: Switch to SATA Identify to check if disk is responding and add Identify/Capacity decoding.
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With SATA Disk:
litex> sata_init
Initialize SATA...
Model: KINGSTON SA400S37240G
Capacity: 240GB
Successful.
Without SATA Disk:
litex> sata_init
Initialize SATA... Failed.
2022-05-18 18:01:54 +02:00
04f6b17d03
build: Remove openfpga build backend (Replaced by osfpga build backend).
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OpenFPGA build backend was an experimental build backend for OpenFPGA/SOFA chips.
OpenFPGA is now providing a new FOEDAG build framework abstracting things and providing
a regular .tcl/.sdc based toolchain.
2022-05-18 15:36:30 +02:00
aaf03b3860
soc/add_sata: Integrate LiteSATAIdentify module.
2022-05-18 15:27:13 +02:00
5df1f5f511
soc/add_sata: Add IRQ support.
2022-05-18 15:05:00 +02:00
5c617d139c
Add initial CVA5 support
2022-05-17 20:19:17 -04:00
4401b5a5e8
build/osfpga: Remane FOEDAGToolchain to OSFPGAToolchain and add Foedag/Raptor support through toolchain parameter.
2022-05-17 19:42:26 +02:00
f16f8e5f9e
software/demo/README: Update --build-path (Thanks @mzau).
2022-05-17 19:25:11 +02:00
4810cc15da
soc/LiteXSoCArgumentParser: Fix --cpu-type parsing.
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Could still be improved.
2022-05-17 19:15:06 +02:00
71a5ef2380
build: Add initial OSFPGA/FOEDAG build backend and blinky example.
2022-05-16 16:26:27 +02:00
b020d4cf62
cores/video/VideoTerminal: Avoid downloading font is present locally.
2022-05-12 16:08:42 +02:00
7e1d2bdf9b
cores/video/VideoHDMIPHY: Rework Fake Differential support and automatically detect when required.
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- Detect activation from passed pads: If p and n present -> Activate.
- Make code a bit more generic to avoid if/else.
- Keep change self contained to VideoHDMIPHY to avoid propagating features to VideoHDMI10to1Serializer.
(Less optimal in term of resources since doubling the serializers, but should be negligible and we are
fixing a hardware issue here...).
2022-05-12 16:07:31 +02:00
8fd96cab84
Merge pull request #1290 from swetland/hdmi
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cores/video: VideoHDMIPHY: enable driving both + and - diff outs
2022-05-12 15:08:45 +02:00
50830da636
tools/litex_sim: Use LiteXSoCArgumentParser.
2022-05-12 11:56:33 +02:00
aa8932dd4f
integration/builder/soc: Add get_build_name method (Useful now that builder is no longer called automatically without --build).
2022-05-12 11:56:08 +02:00
e451a87617
cpu/rocket: add 1-core full (fpu) wide-bus variants
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- 1-core "full" (fpu-enabled) variants with double, quad mem. bus width
2022-05-10 19:35:51 -04:00
479773418d
tools/litex_soc_gen: Add identifier, move wb_region to IOs and add optional debug.
2022-05-10 15:16:58 +02:00
48b523cf7e
add cva6 cpu
2022-05-09 21:12:08 +02:00
51c5438c11
cpu/firev: Make name consistent with other CPUs.
2022-05-09 18:23:53 +02:00
7f703dd18f
Merge pull request #1293 from enjoy-digital/fhdl_namer_changes
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FHDL Namer integration and memory .init naming improvements.
2022-05-09 18:22:42 +02:00
6d36fd2dda
gen/fhdl/namer: Minor cleanup to ease readability.
2022-05-09 17:53:27 +02:00
974d15d8c0
Merge pull request #1292 from zeldin/vexriscv_crt_fix
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cpu/vexriscv: Fix compilation of crt0.S with new binutils.
2022-05-09 14:22:49 +02:00
2db57d4be3
interconnect: Add name parameter to Wishbone/AXI SRAMs nad use it in add_ram to improve generated memory names.
2022-05-09 10:29:15 +02:00
7370a9fe6f
fhdl/memory/namer: Improve readability.
2022-05-09 10:22:48 +02:00
a0f0ea4842
cpu/vexriscv: Fix compilation of crt0.S with new binutils.
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The csrw opcode is no longer part of the "I" instruction set but has
been moved to a separate extension. Enable that extension in crt0.S.
2022-05-08 18:54:23 +02:00
3a388d1f19
fhdl/memory: Prefix memory files with build name.
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This simplify re-integrating pre-generated SubSoCs in a top level SoC.
2022-05-06 20:21:30 +02:00
7800858c7a
gen/fhdl/namer: Cleanup & add comments on Namespace.
2022-05-06 20:07:35 +02:00
61eead5170
fhdl/memory/verilog: Rename ns -> namespace and minor cleanup.
2022-05-06 19:34:21 +02:00
b83e84c78a
gen/fhdl: Integrate namer from Migen to give us more flexibility on generated verilog names.
2022-05-06 16:04:24 +02:00
79d0e0916a
CHANGES: Update.
2022-05-06 15:16:48 +02:00
3f101a3520
CHANGES: Update.
2022-05-06 13:43:39 +02:00
a8c48b42f9
Merge pull request #1281 from antmicro/i2s_f4pga_fix
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Add LiteX equivalent of Xilinx FIFO_SYNC_MACRO to I2S
2022-05-06 09:10:22 +02:00
0a1ae7b413
setup.py: Expose litex_soc_gen and litex_periph_gen and sort console scripts.
2022-05-05 17:44:59 +02:00
e8b6200225
tools: Add initial LiteX standalone SoC generator.
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Allow generating standalone SoC with CPU/Peripherals that can be re-integrated in
external design or top level LiteX SoCs.
Example of of use:
python3 litex_soc_gen.py --cpu-type=vexriscv --bus-standard=wishbone --build
python3 litex_soc_gen.py --cpu-type=naxriscv --bus-standard=axi-lite --build
2022-05-05 17:36:34 +02:00
enjoy-digital
Jevin Sweval
Tony McDowell
Massimiliano Giacometti
Eric Matthews
Gabriel Somlo
Dolu1990
Marcus Comstedt