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72 commits 42 branches 14 tags 31 MiB
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67 commits

Author SHA1 Message Date
Florent Kermarrec
c28067d672 link: test RX path 2014-12-05 20:26:09 +01:00
Florent Kermarrec
b238c41b26 link_tb: use LinkTXPacket and LinkRXPacket from bfm 2014-12-05 18:00:02 +01:00
Florent Kermarrec
e900b9031c move test 2014-12-05 17:48:01 +01:00
Florent Kermarrec
6f96338962 bfm: add FIS decoding/encoding 2014-12-05 01:13:55 +01:00
Florent Kermarrec
9da1f7fcbb bfm: rewrite it and split Physical / Link layers 2014-12-04 23:43:21 +01:00
Florent Kermarrec
6e6243e983 transport: define FIS layouts 2014-12-03 16:53:20 +01:00
Florent Kermarrec
ddd4b65f44 link: split SATALinkLayer in SATALinkLayerTX and SATALinkLayerRX 2014-12-03 15:29:01 +01:00
Florent Kermarrec
d3974882e4 link: manage CONT on RX path 2014-12-03 11:50:31 +01:00
Florent Kermarrec
47a5a9529b link: manage CONT on TX path 2014-12-03 11:12:26 +01:00
Florent Kermarrec
cab5b7b8f8 link: simplify BFM 2014-12-03 09:17:51 +01:00
Florent Kermarrec
6cc8686402 link: manage hold 2014-12-03 02:06:43 +01:00
Florent Kermarrec
ed97f378ff link: add CRC check to BFM 2014-12-02 20:02:43 +01:00
Florent Kermarrec
f2757ef8dd link: fix link_tb (due to others modifications) 2014-12-02 19:53:13 +01:00
Florent Kermarrec
31b9132dd9 link: improve and clean up crc_tb, scrambler_tb 2014-12-02 19:24:46 +01:00
Florent Kermarrec
2b7779d3b6 link: wip bfm 2014-11-12 18:20:34 +01:00
Florent Kermarrec
b423c1df4b link: prepare simulation 2014-11-11 18:47:34 +01:00
Florent Kermarrec
64ed34b35a clean up 2014-11-11 16:15:28 +01:00
Florent Kermarrec
705819f885 use new EndpointDescription 2014-11-11 14:54:54 +01:00
Florent Kermarrec
67aaf09b53 link: SATALinkLayer skeleton 2014-11-11 12:29:37 +01:00
Florent Kermarrec
294855e292 phy: use primitives dict and use only sata.std 2014-11-11 10:19:24 +01:00
Florent Kermarrec
30964db4a1 phy: send 2 ALIGN primitives every 256 DWORDs 2014-11-11 09:57:43 +01:00
Florent Kermarrec
353e7fc13b link: add SATALinkLayer skeleton (wip) 2014-11-04 22:55:31 +01:00
Florent Kermarrec
8f6354f2a3 link: improve crc_tb/ preamble_tb and increase length 2014-11-04 17:06:03 +01:00
Florent Kermarrec
c810009387 link: add Scrambler and testbench 2014-11-04 16:40:21 +01:00
Florent Kermarrec
8062298668 link: add CRC and testbench 2014-11-04 10:33:11 +01:00
Florent Kermarrec
449daedab7 sata/link: add crc and scrambler C models from SATA specification 2014-11-03 18:11:14 +01:00
Florent Kermarrec
47b5ff5e33 move code and create a directory for each layer 2014-11-03 17:38:12 +01:00
Florent Kermarrec
25e0ccae9a remove DRP ports (won't be used for now) 2014-10-28 11:33:15 +01:00
Florent Kermarrec
3f7406a937 various fixes and simplifications, SATA1 & SATA2 OK 2014-10-28 02:15:19 +01:00
Florent Kermarrec
bbfce2b707 ctrl: drive txcomwake and not gtx.txcomwake in K7SATAPHYDeviceCtrl 2014-10-16 10:38:26 +02:00
Florent Kermarrec
110580eb2e add .payload. to Sink and Source to be compatible with upstream Migen 2014-09-30 11:03:36 +02:00
Florent Kermarrec
f5001751d0 instanciate GTXE2_COMMON (seems recommended in AR43339) 2014-09-30 10:57:52 +02:00
Florent Kermarrec
d47917e480 simplify and clean up 2014-09-30 00:50:03 +02:00
Florent Kermarrec
0791b9e2e4 sim working 2014-09-29 17:12:02 +02:00
Florent Kermarrec
b47153fbfa fix alignment (still some transmissions errors --> need to check clocks and resets) 2014-09-29 15:37:35 +02:00
Florent Kermarrec
ed752758b0 fix and simplify ctrl fsms, OOB OK, align KO 2014-09-27 17:45:46 +02:00
Florent Kermarrec
2f769e4e4e gtx: add resynchronization on control signals 2014-09-27 17:26:05 +02:00
Florent Kermarrec
f23c5aa724 mmcm: configure default divider with default_speed 2014-09-27 16:22:40 +02:00
Florent Kermarrec
45f7f8aff5 add tx_reset_fsm and rx_reset_fsm 2014-09-27 16:10:39 +02:00
Florent Kermarrec
c27f24c4c0 reorganize code 
- use sys_clk of 166.66MHz and using it instead of sata clk.
- rename clocking to CRG since it also handles resets.
- create datapath and move code from gtx.
 2014-09-27 15:34:28 +02:00
Florent Kermarrec
879478a6e4 clocking: clean up and add comments 2014-09-27 13:33:43 +02:00
Florent Kermarrec
387cf90cf8 host and device communicate with OOB, now need to fix ctrl 2014-09-26 23:30:30 +02:00
Florent Kermarrec
01da43ecb2 reset and lock of PLL OK. We see OOB signals on the link but they are not decoded by the device. 2014-09-26 22:31:32 +02:00
Florent Kermarrec
dfbec91a62 add modelsim simulation and start fixing init 2014-09-26 17:05:05 +02:00
Florent Kermarrec
7e14c4fc51 move some logic outside of GTX 2014-09-25 15:23:56 +02:00
Florent Kermarrec
c008dfdd98 clean up (thanks to Sebastien) 2014-09-25 14:17:25 +02:00
Florent Kermarrec
435bc22fa0 integrate phy in test design and start fix syntax errors 2014-09-24 16:07:34 +02:00
Florent Kermarrec
18009303ae instanciate device or host controller 2014-09-24 14:00:00 +02:00
Florent Kermarrec
60324295fa manage clock domain crossing and data width conversion in gtx 2014-09-24 13:56:12 +02:00
Florent Kermarrec
f436069a04 create sata clock (sata_tx/2 for a 32 bits data path) 2014-09-24 13:55:06 +02:00