3ebe877fd2
use similar names for wishbone bridges and move wishbone drivers to [core]/software
2015-05-02 16:22:30 +02:00
c03c41eb77
litescope: rename host directory to software (to be coherent with others cores)
2015-05-01 20:45:02 +02:00
1281a463d6
litescope/bridge: create a generic wishbone bridge that can be used with different phys (the phy needs to provide a sink/source with 8bits data).
...
- we can now pass a phy to LiteScopeWishboneBridge
- LiteScopeUART2Wishbone is only a specific LiteScopeWishboneBridge
- UART mux is removed since complicated and no longer useful (we can now create easily virtual UART over Ethernet, USB or PCIe) or simply add another UART for debug.
2015-05-01 17:51:18 +02:00
5a930fe7cf
lite* cores: changes permissions (+x) on make.py files and on litepcie init.sh file
2015-04-18 08:51:59 -04:00
1f19e6ae92
litesata: pep8 (E265)
2015-04-13 15:58:58 +02:00
c8bcbfb855
litesata: pep8 (E261, E271)
2015-04-13 15:51:17 +02:00
ea67080462
litesata: pep8 (E225)
2015-04-13 15:44:04 +02:00
77cdb953ad
litesata: pep8 (E401)
2015-04-13 15:27:36 +02:00
8f7751e412
litesata: pep8 (E203)
2015-04-13 15:25:40 +02:00
d0c5bd377a
litesata: pep8 (E302)
2015-04-13 15:12:39 +02:00
808e1fe866
litesata: pep8 (replace tabs with spaces)
2015-04-13 14:59:00 +02:00
9107710f03
litexxx cores: use default baudrate of 115200 for all tests
2015-03-20 12:22:53 +01:00
236ea0f572
liteeth: use bios ip_address in example designs
2015-03-18 18:18:43 +01:00
a266deb58e
LiteXXX cores: fix frequency print in test/test_regs.py
2015-03-17 16:01:25 +01:00
d2cb41bc63
LiteXXX cores: convert port parameter to int if is digit in test/make.py
2015-03-17 15:58:21 +01:00
52f1c45407
LiteXXX cores: fix test_reg.py
2015-03-04 23:13:14 +01:00
1d4dc45436
LiteXXX cores: use format in prints
2015-03-03 10:29:28 +01:00
67ca0da1d9
liteXXX cores: share same methodology for on-board tests
2015-03-01 11:21:12 +01:00
0dfca49e68
litesata: move file and modify import to misoclib.mem.litesata
2015-02-28 11:03:24 +01:00
Florent Kermarrec