c0c5ae558a
build/generic_programmer: move requests import to do it only when needed.
2020-04-16 08:44:36 +02:00
c9ab593989
bios/sdram/ECP5: set ERR_DDRPHY_BITSLIP to 4.
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Bitslip software control is now used on ECP5 to move dqs_read.
2020-04-15 19:30:28 +02:00
2d01882653
setup.py/install_requires: add requests.
2020-04-15 09:27:26 +02:00
5e149ceda2
build/generic_programmer: add automatic search/download of flash_proxy in repositories if not available locally.
2020-04-15 08:59:03 +02:00
a298a9e568
Merge pull request #467 from antmicro/region_type_fix
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soc_core: Fix region type generation
2020-04-15 07:56:48 +02:00
77a05b78e8
soc_core: Fix region type generation
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Include information about being a linker region.
2020-04-14 21:45:32 +02:00
d44fe18bd9
stream/AsyncFIFO: add default depth (useful when used for CDC).
2020-04-14 17:35:19 +02:00
ded10c89dc
build/sim/core/Makefile: add -p to mkdir modules.
2020-04-14 12:38:02 +02:00
c323e94c83
Merge pull request #464 from mithro/litex-sim-fixes
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Improve the litex_sim Makefiles
2020-04-14 12:16:21 +02:00
a8bf02167a
litex_setup: raise exception on update if repository has been been initialized.
2020-04-12 19:46:56 +02:00
97d0c525ee
Remove trailing whitespace.
2020-04-12 10:29:13 -07:00
4fe31f0760
cores: add External Memory Interface (EMIF) Wishbone bridge.
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Useful to interface Processors/DSPs with LiteX. EMIF is generally used on Texas Instrument DSPs.
2020-04-12 16:34:33 +02:00
44746870a7
Merge pull request #462 from ironsteel/trellis-12k
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Add support for ecp5 12k device in trellis.py
2020-04-12 15:49:49 +02:00
c57e438df6
boards/targets/ulx3s.py: Update --device option help message
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Signed-off-by: Rangel Ivanov <rangelivanov88@gmail.com>
2020-04-12 12:01:31 +03:00
f4b345ecd7
build/lattice/trellis.py: Add 12k device
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nextpnr adds the --12k option which is the same like
the --25k but with the correct idcode for the 12k devices
Signed-off-by: Rangel Ivanov <rangelivanov88@gmail.com>
2020-04-12 11:46:44 +03:00
1f35669508
litex_sim: Find tapcfg from pythondata module.
2020-04-11 18:38:15 -07:00
3aee8a5227
Remove directories from submodules from MANIFEST.in file.
2020-04-11 18:37:06 -07:00
ebcb2a4406
Rename litex-data-XXX-YYY to pythondata-XXX-YYY
2020-04-11 18:37:06 -07:00
a39a4ec2ed
Only allow fast-forward pulls.
2020-04-11 18:37:06 -07:00
e618d41ffb
Fixing mor1kx data finding.
2020-04-11 18:37:06 -07:00
2e3b7f20c7
Fix typo in error message.
2020-04-11 18:37:06 -07:00
83b2581331
Fix the libcompiler_rt path.
2020-04-11 18:37:06 -07:00
1c1c5bcbda
Remove submodules.
2020-04-11 18:37:06 -07:00
c96d1e6672
Fix import for data.
2020-04-11 18:37:06 -07:00
119985f353
Use the current directory you are running.
2020-04-11 18:37:06 -07:00
69367f8d4e
Make litex a namespace.
2020-04-11 18:37:06 -07:00
3ae4f8f2de
Adding missing vexriscv CPU.
2020-04-11 18:37:06 -07:00
ac3fd794f9
Adding missing comma.
2020-04-11 18:37:06 -07:00
3df6c0c8a2
Adding litex-data-software-compiler_rt as a required package.
2020-04-11 18:37:06 -07:00
3964565e15
Fixed quotes in `litex_setup.py`
2020-04-11 18:37:06 -07:00
d5a21a7522
Converting litex to use Python modules.
2020-04-11 18:37:06 -07:00
5a0bb6ee01
litex_sim: Rework Makefiles to put output files in gateware directory.
2020-04-11 18:37:03 -07:00
a0658421cc
litex_sim: Better error messages on failure to load module.
2020-04-11 18:35:39 -07:00
d0d2f2824b
README: LiteDRAM moved to travis-ci.com as others repositories.
2020-04-10 19:11:21 +02:00
b95e0a19b1
altera/common: add DDROutput, DDRInput, SDROutput, SDRInput.
2020-04-10 15:50:35 +02:00
40f43efcf6
targets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets.
2020-04-10 14:41:01 +02:00
292d6b75b6
build/xilinx/common: add Spartan6 specialized DDRInput, SDROutput, SDRInput and SDRTristate.
2020-04-10 14:38:22 +02:00
88dc5158c1
build/io: add SDR Tristate (with infered version) and remove multi-bits support on SDRIO.
2020-04-10 14:37:29 +02:00
fdadbd868b
build/lattice/common: remove multi-bits support on SDRInput/Output.
2020-04-10 14:36:13 +02:00
8159b65bee
litex/build/io: also import CRG (since using DifferentialInput).
2020-04-10 10:25:21 +02:00
79913e8614
litex.build: update from migen.genlib.io litex.build.io.
2020-04-10 09:49:45 +02:00
8e014f76da
litex/build: move io.py from litex/gen and re-import DifferentialInput/Output, DDRInput/Output contributed to Migen.
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This will make things easier and more consistent, all special IO primitives are now in LiteX.
2020-04-10 08:47:07 +02:00
2e270cf28c
platforms/versa_ecp5: remove Lattice Programmer (no longer used since we can now use OpenOCD).
2020-04-09 23:08:59 +02:00
deebc49ab0
boards/platforms: cosmetic cleanups.
2020-04-09 23:04:29 +02:00
3c0ba8ae62
boards/plarforms/ulx3s: cleanup, fix user_leds, add spisdcard, add PULLMODE/DRIVE on SDRAM pins.
2020-04-09 18:55:01 +02:00
6c429c9995
build/lattice: add ECP5 implementation for SDRInput/SDROutput.
2020-04-09 16:24:05 +02:00
72c8d590fa
litex/gen: add io with SDRInput/SDROutput (if not overrided, register is supposed to be infered).
2020-04-09 16:23:27 +02:00
8f57321f30
tools/litex_sim: remove LiteSPI support for now since breaking Travis-CI of others sub-projects.
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LiteSPI is not mature enough to be integrated in LiteX sim directly. (will case trouble is things are refactored).
This could be re-introduced later when more mature. For now simulation with LiteX Sim
could be tested directly in LiteSPI with a custom simulation.
2020-04-09 11:14:19 +02:00
9afd017a3a
tools/litex_term: increase workaround delay for usb_fifo. (validated on Minispartan6 and MimasA7).
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Still needs to be fixed properly.
2020-04-09 10:52:15 +02:00
fdfede2281
Merge pull request #459 from mithro/travis-fix
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Two small Travis-CI related patches
2020-04-09 09:01:59 +02:00
Florent Kermarrec
Mateusz Holenko
Tim 'mithro' Ansell
Rangel Ivanov