Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
5,597 Commits 40 Branches 14 Tags 26 MiB
Commit Graph

5597 Commits

Author SHA1 Message Date
Florent Kermarrec 9c8c037108 soc_zynq: move axi gp0 clock connection to add_gp0 method 2019-07-10 16:50:06 +02:00
Florent Kermarrec b0192e5f8b soc_core: use fixed 16MB CSR address space 
Using too small CSR address space cause a regression on PCIe SoC, this would
need to be understood if we want to reduce CSR address space under 16MB.
 2019-07-10 10:39:00 +02:00
Florent Kermarrec 68a503174c soc_sdram: limit main_ram to 512MB for now 
Otherwise breaks linux-on-litex-vexriscv for targets with 1GB of ram, could
be removed when mem_map will be reworked on linux-on-litex-vexriscv.
 2019-07-09 12:14:50 +02:00
Florent Kermarrec ccbf141850 compiler-rt: update to new location, fixes #209 2019-07-08 23:03:23 +02:00
Florent Kermarrec 21a5aaa4a6 soc_core: declare csr address size when registering csr, fixes #212 2019-07-08 22:58:07 +02:00
Florent Kermarrec 41b6fbde42 soc_cores: fix typos 2019-07-08 22:56:14 +02:00
enjoy-digital bff081a818
Merge pull request #214 from gsomlo/gls-alignment-fixup 
soc_core: additional csr_alignment follow-up fixes
 2019-07-08 19:03:28 +02:00
Gabriel L. Somlo e42f33ede1 soc_core: additional csr_alignment follow-up fixes 
- Update a few additional places to use DFII_ADDR_SHIFT instead of
  a hard-coded 4, which assumed 32-bit alignment.

- Force 64-bit alignment Rocket -- the only supported configuration!

This is a fixup for commit f4770219, tested on Rocket and 64bit Linux.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-07-08 10:15:14 -04:00
Florent Kermarrec f4770219fa soc_core: add csr_alignment to allow 64-bit alignment with 64-bit CPUs 2019-07-08 10:20:51 +02:00
Florent Kermarrec 927b7c13a2 soc/integration: uniformize configuration constants declaration in SoCs (use self.config instead self.add_constant) 2019-07-08 08:57:05 +02:00
Florent Kermarrec 96f45bbd87 software/libbase/id: update code (length is now fixed to 256) 2019-07-06 17:18:34 +02:00
Florent Kermarrec 282ae96354 cores: add simple PWM (Pulse Width Modulation) module 2019-07-05 19:39:08 +02:00
Florent Kermarrec 77e7f9b3c1 core/spi: make cs_n optional (sometimes managed externally) 2019-07-05 19:18:52 +02:00
Florent Kermarrec e726ad80ac cores/spi_flash: add non-memory mapped S7SPIFlash modules based on SPIMaster (for design were we only want to re-program the bistream) 2019-07-05 19:01:55 +02:00
Florent Kermarrec 4c18c991bc cores: add ICAP core (tested with reconfiguration commands) 2019-07-05 18:30:34 +02:00
Florent Kermarrec 6b82f23ce1 cores: add simple and minimal hardware SPI Master with CPOL=0, CPHA=0 and build time configurable data_width and frequency. 2019-07-05 15:50:58 +02:00
Florent Kermarrec ada70e8c52 soc/cores/spi: remove too complicated and does not seem reliable in all cases. 2019-07-05 14:38:09 +02:00
Florent Kermarrec 7cd5c0f39b cores: add bitbang class with minimal hardware for I2C/SPI software bit-banging 2019-07-05 14:26:10 +02:00
Florent Kermarrec d29b841997 cores: remove nor_flash_16 (obsolete, most of the boards are now using SPI flash) 2019-07-05 13:13:31 +02:00
Florent Kermarrec 3f6bd266d9 cores/gpio: remove Blinker 2019-07-05 13:09:21 +02:00
Tim Ansell 359b8fe4bb
Merge pull request #210 from DurandA/master 
Add verilog submodule from CPU cores to manifest
 2019-07-03 17:23:36 -07:00
Arnaud Durand 68eeba9181
Add verilog submodule from CPU cores to manifest 2019-07-04 00:58:26 +02:00
Florent Kermarrec 4ee9c53f18 csr: add assert to ensure CSR size < busword (thanks tweakoz) 2019-07-03 13:44:15 +02:00
Florent Kermarrec 0116b2b708 soc_core: update default RocketChip mem_map 2019-06-28 23:40:01 +02:00
Florent Kermarrec 9d170b0944 soc_core: rearrange default mem_map 2019-06-28 23:27:23 +02:00
Florent Kermarrec 05b667bb95 bios/main: fix #ifdefs for fw command 2019-06-28 22:42:02 +02:00
Florent Kermarrec 37687579e0 libnet/tftp: fix compilation warning 2019-06-28 22:32:45 +02:00
Florent Kermarrec 9f3c8a9b8a bios/main: fix spiflash compilation warnings 2019-06-28 22:18:24 +02:00
Florent Kermarrec 2da59b29e2 soc_sdram: allow main_ram_size > 256MB (limitation no longer exists) 2019-06-28 22:10:25 +02:00
Florent Kermarrec b8d45af5c3 targets: use new prefered way to add wishbone slave 2019-06-28 22:10:20 +02:00
Florent Kermarrec 7618b84533 soc_core: use new way to add wisbone slave (now prefered) 2019-06-28 22:10:15 +02:00
Florent Kermarrec 740629ba53 soc_core: remove 256MB mem_map limitation 
mem_map was limited to 8 256MB for simplicity but has become an issue for
complex SoCs. Default mem_map size is still 256MB (retro-compatibility) but
size can now be specified.
 2019-06-28 22:10:02 +02:00
Florent Kermarrec b65968c329 soc/core: remove #!/usr/bin/env python3 2019-06-28 21:37:52 +02:00
enjoy-digital f49d0fe6c9
Merge pull request #206 from gsomlo/gls-tftp-spinner 
BIOS: TFTP: ASCII spinner progress indicator (cosmetic)
 2019-06-27 17:02:29 +02:00
Gabriel L. Somlo 5a42dbf333 BIOS: TFTP: ASCII spinner progress indicator (cosmetic) 2019-06-27 10:31:33 -04:00
enjoy-digital d5177d72ac
Merge pull request #204 from antmicro/write_to_flash 
fw (flash write) command
 2019-06-25 19:10:17 +02:00
Florent Kermarrec cef2369015 core/spi_flash: re-integrate bitbang write support 2019-06-25 19:09:30 +02:00
Mateusz Holenko 2ee194b259 bios: add fw (flash write) command 2019-06-25 16:58:12 +02:00
Florent Kermarrec 5cc4c334d6 README: remove LiteUSB (deprecated) 2019-06-24 15:41:22 +02:00
Florent Kermarrec dc03b7fab9 boards: community supported boards are now located at https://github.com/litex-hub/litex-boards 2019-06-24 12:05:02 +02:00
Florent Kermarrec 0af017e67c liteeth: update mac imports (olds still works, but that's now the prefered way) 2019-06-24 11:45:01 +02:00
Florent Kermarrec ecf999b8c7 soc/cores: add usb_fifo with FT245 USB FIFO PHY from LiteUSB, deprecate LiteUSB 
LiteUSB was not up to date was not a real USB PHY but was just providing USB FIFO PHYs.
New true USB cores are now available: Daisho, ValentyUSB, so it's better using
then for true USB support. We only keep the FT245 FIFO PHY in LiteX that can be
useful to interface with USB2/USB3 USB FIFOs.
 2019-06-24 10:58:36 +02:00
Florent Kermarrec e667d5ae53 README: update Intro 2019-06-24 09:59:10 +02:00
Florent Kermarrec 8f6e66ca52 make sure #!/usr/bin/env python3 is before copyright header 2019-06-24 07:29:24 +02:00
Florent Kermarrec c7f36ab08f test: add copyright header 2019-06-23 23:31:11 +02:00
Florent Kermarrec daa4307d9e add CONTRIBUTORS file and add copyright header to all files 2019-06-23 23:23:56 +02:00
Florent Kermarrec 361f9d0dff bios/sdram: set init_done/error when DDRCTRL is present (litedram_gen) 2019-06-22 10:55:15 +02:00
Tim 'mithro' Ansell d8ac936206 Convert top level comment to a docstring. 2019-06-21 12:03:30 -07:00
enjoy-digital 45632c66b1
Merge pull request #202 from xobs/add-up5kspram 
soc: cores: add up5kspram module
 2019-06-21 10:26:07 +02:00
William D. Jones 7656f54d0a soc: cores: add up5kspram module 
The ICE40UP5K has 128 kB of SPRAM that's designed to be used
as memory for a softcore.  This memory is actually 4 16-bit
chunks that we can gang together to give us either 64 kB or
128 kB.

Add a module that will allow us to use this memory in an ICE40.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-06-20 11:12:46 -07:00