c19c343ecf
software/libbase: add memtest_access before testing bus/addr/data to exit early if bus errors are detected.
2020-12-07 14:05:51 +01:00
fb05fbc5cc
software: always provide flush_l2_cache implementation (even if empty) to avoid #ifdefs CONFIG_L2_SIZE.
2020-12-07 13:45:05 +01:00
3ce74f6e29
software/libbase/memtest: cosmetic cleanups.
2020-12-07 13:23:58 +01:00
9af9ee6b66
soc/interconnect/axi: let connect_to_pads() be used by AXIInterface too
2020-12-06 00:23:30 +01:00
bed072ef19
tools/litex_term: use different payload_length/delay settings for USB-ACM.
2020-12-04 19:59:49 +01:00
d8b844bbda
tools/litex_json2dts: Group tuples in liteeth reg property
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To improve human readability and enable automatic validation, the tuples
in "reg" properties should be grouped using angle brackets.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2020-12-04 16:38:48 +01:00
a17b535906
tools/litex_json2dts: Fix DTS indentation
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Make indentation of the generated DTS more consistent, by always using 8
spaces (no TABs), and aligning continued lines.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2020-12-04 16:21:52 +01:00
8265d06728
tools/litex_json2dts: Fix SPI bus #size-cells
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As per Documentation/devicetree/bindings/spi/spi-controller.yaml,
"#size-cells" must be zero for a PCI bus.
This gets rid of the following build warnings:
build/orangecrab/orangecrab.dts:105.29-39: Warning (reg_format): /soc/spi@f0004800/mmc-slot@0:reg: property has invalid length (4 bytes) (#address-cells == 1, #size-cells == 1)
buildroot/rv32.dtb: Warning (pci_device_reg): Failed prerequisite 'reg_format'
buildroot/rv32.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format'
buildroot/rv32.dtb: Warning (simple_bus_reg): Failed prerequisite 'reg_format'
buildroot/rv32.dtb: Warning (i2c_bus_reg): Failed prerequisite 'reg_format'
build/orangecrab/orangecrab.dts:91.46-110.19: Warning (spi_bus_bridge): /soc/spi@f0004800: incorrect #size-cells for SPI bus
buildroot/rv32.dtb: Warning (spi_bus_reg): Failed prerequisite 'reg_format'
buildroot/rv32.dtb: Warning (spi_bus_reg): Failed prerequisite 'spi_bus_bridge'
Fixes: fafa844aa7
2020-12-04 16:19:29 +01:00
b7c0922ec1
tools/litex_term: increase outstanding to 128 (4 is slowing down speed with USB-FIFO).
2020-12-04 16:01:35 +01:00
894802d131
tools/litex_term: add sfl_outstanding parameter (set to 4), cleanup code and increase inter-frame delay.
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This fixes upload on OrangeCrab with USB-ACM, but we still need to understand why
sfl_payload_length can't be set to 255 with USB-FIFO.
2020-12-04 15:46:18 +01:00
5e10552f3f
soc/interconnect/packet/Packetizer: fix last_be for 10gbe.
2020-12-03 17:11:04 +01:00
168c5380cf
Merge pull request #718 from trabucayre/zynq_fix_constraints
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don't add pins without pad location in constraints file
2020-12-03 16:21:06 +01:00
88023394fd
Merge pull request #721 from daveshah1/dave/nexus-pll-resetena
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clock/lattice_nx: Set PLLRESET_ENA parameter
2020-12-03 15:54:16 +01:00
dba6653cb4
tools/litex_term: reduce sfl_payload_length to 64 as before.
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See: https://github.com/enjoy-digital/litex/issues/720 .
2020-12-03 12:52:00 +01:00
90315868a8
clock/lattice_nx: Set PLLRESET_ENA parameter
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If this parameter isn't set to ENABLED; then the PLLRESET signal is
ignored.
Signed-off-by: David Shah <dave@ds0.me>
2020-12-03 11:49:48 +00:00
172dc18dfb
bios/boot: remove SFL_CMD_LOAD_NO_CRC support (non longer useful since CRC checking is now fast).
2020-12-03 12:11:48 +01:00
136db6a0ca
Merge pull request #719 from davidlattimore/no-error-recovery
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lxterm: Speed up CRC checked uploads
2020-12-03 12:06:46 +01:00
d6a49e85c4
integration/soc_core: only add IRQs from interrupt_map if SoC supports them.
2020-12-03 09:48:42 +01:00
42e7b8d35a
integration/soc/irq: improve error message.
2020-12-03 09:47:50 +01:00
b421d50b40
lxterm: Increase maximum payload size to match BIOS
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sfl_frame (in sfl.h) already had a payload size of 255.
This should give about a 10% speed gain due to reduced overhead. 8 bytes
of header per 251 bytes sent, as opposed to 8 bytes of header per 60
bytes sent
2020-12-03 13:44:09 +11:00
03c2257baf
lxterm: Deprecate --no-crc flag
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The flag is left, in case people are using it from scripts, but now does
nothing besides printing a warning.
2020-12-03 13:37:43 +11:00
513a799a39
lxterm: Don't attempt to recover from CRC errors during upload.
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This allows transfers to proceed at the full speed of the serial link.
We still check all responses, but will now fail outright if a CRC error
occurs.
2020-12-03 13:37:26 +11:00
b896b20e46
don't add pins without pad location in constraints file
2020-12-02 13:24:15 +01:00
8eecbd7b57
integration/soc/add_sdcard: integrate interrupts.
2020-12-01 13:25:05 +01:00
2e7203d930
Merge pull request #716 from gsomlo/gls-irq-misc
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miscellaneous (mostly cosmetic) soc irq init fixes
2020-12-01 08:29:05 +01:00
5cc3db0176
soc: cosmetic: reduce horizontal indentation in IRQ init.
2020-11-30 16:29:16 -05:00
9af56cf247
soc: fix typo in IRQ handler exception
2020-11-30 16:27:31 -05:00
d193092e16
cores/cpu/cv32e40p/core: rewrite OBI2Wishbone to reduce write/read latency by 1 cycle.
2020-11-30 12:18:59 +01:00
18f66a79f2
cores/cpu/zynq7000: improve methods to pass provide/pass configuration to PS7.
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User can now only use set_ps7 and provides the .xci file, preset file or/and additional configuration:
To use a .xci file, in the design do:
self.cpu.set_ps7(xci="ps7.xci")
To use a preset:
self.cpu.set_ps7(preset="preset_name")
To use a config dict:
self.cpu.set_ps7(name="ps7_name", config={"param0": "0", "param1": "1"})
It's also possible to use preset and then pass and additionnal config dict:
self.cpu.set_ps7(preset="preset_name")
self.cpu.add_ps7_config({"param0": "0", "param1": "1"})
or all at once:
self.cpu.set_ps7(preset="preset_name", config={"param0": "0", "param1": "1"})
2020-11-30 11:30:48 +01:00
30e8773819
Merge pull request #711 from trabucayre/ps7_config
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zynq7000: add tcl to create zynq IP based on board preset and custom configuration
2020-11-30 10:28:54 +01:00
c8fcaaea2d
integration/soc: use self.irq.enabled instead of hasattr(self.cpu, "interrupt").
2020-11-30 10:17:03 +01:00
146068b048
integration/soc/SoCIRQHandler: be sure IRQs can only be added when enabled.
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This prevents adding peripherals that requires IRQ support to SoC not supporting
them. Enabling is done automatically when a CPU with interrupt support is added,
but this can also be added manually.
2020-11-30 10:06:45 +01:00
d9f9b4aeb6
Merge pull request #713 from daveshah1/dave/rocket-reset-fix
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rocket: Fix UB due to optimised away DFFs
2020-11-28 08:12:33 -05:00
61895bef37
rocket: Fix UB due to optimised away DFFs
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As both clock and async reset for the debug DFFs were 0, and there was
no initial value on them, they were being validly optimised away by
newer Yosys versions to 1'bx which was propagating into and breaking the
core.
This fixes the problem by tying the async resets to the CPU reset
signal.
Signed-off-by: David Shah <dave@ds0.me>
2020-11-28 11:15:42 +00:00
c491c60b7d
soc/cores/prbs/PRBSRX: add pause signal to pause errors counting.
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Simplify CDC when passing the errors to software by allowing the values to stabilized.
2020-11-28 11:33:57 +01:00
869e50ade8
soc/cores/prbs: minor cosmetic cleanups.
2020-11-28 10:27:22 +01:00
e2dcdcf917
build/lattice/programmer/load_bitstream: convert .bit to .svf with bit_to_svf it bitstream_file provided as .bit.
2020-11-28 08:58:57 +01:00
289234b102
build/lattice: add bit_to_svf script from Project Trellis to allow using OpenOCD with Diamond.
2020-11-28 08:58:04 +01:00
08b6d0388c
zynq7000: add tcl to create zynq IP based on board preset and custom configuration
2020-11-28 08:56:47 +01:00
785bc7e86c
build/lattice/diamond: set timingstrict default value to False (similar to others build backends)
2020-11-28 07:56:30 +01:00
52a1622895
README: update ci badges.
2020-11-26 19:13:56 +01:00
e5a7375b30
cores/clock/ECP5PLL: ensure ECP5PLL's locked is deasserted on reset.
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It seems EHXPLLL does not loose locked when reseted.
2020-11-26 18:56:24 +01:00
b02753ecfa
tools/comm_udp/litex_server: add --udp-scan args to scan network for available Etherbone/UDP devices.
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litex_server --udp --udp-scan --udp-ip=192.168.1.x --udp-port=1234
Etherbone scan on 192.168.1.x network:
- 192.168.1.20
- 192.168.1.50
2020-11-26 13:33:20 +01:00
4a748a53b8
soc/interconnect/packet: add initial PacketFIFO.
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For now just ensures that we have a full packet in the FIFO before setting source.valid.
It would be nice in the future to also be able to discard packets in the FIFO.
2020-11-26 11:27:42 +01:00
c3660379db
tools/remote/comm_udp: probe Etherbone server on open().
2020-11-26 09:06:52 +01:00
f390161baa
integration/soc/add_ethernet: don't add timing constraints with LiteEthPHYModel.
2020-11-26 09:06:06 +01:00
896d1ba988
Merge pull request #709 from daveshah1/oxide-build
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Add Yosys/nextpnr-nexus/oxide flow for CrossLink-NX
2020-11-25 19:21:11 +01:00
ad62e15d98
tools/litex_server: move PCIe specific bar renaming/enable to comm_pcie.
2020-11-25 16:25:31 +01:00
595c6738a3
tools/remote/etherbone: speed up encoding/decoding.
2020-11-25 16:08:12 +01:00
3d2574a488
tools/remote/comms: base CommXY on CSRBuilder to allow using Comms directly in python scripts.
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This way, user scripts can be use RemoteClient (communicating with the Server that has
already been opened on the right interface) or directly use CommXY in the scripts.
Using RemoteClient is more generic but can be slower (due to the Etherbone encoding between
the client and server). On fixed configuration using CommXY directly can then be faster
and also avoid manual opening of the server.
2020-11-25 15:05:28 +01:00
Florent Kermarrec
Ilia Sergachev
Geert Uytterhoeven
David Shah
David Lattimore
Gwenhael Goavec-Merou
Gabriel Somlo