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Author SHA1 Message Date
Florent Kermarrec
c64129dc69 soc/integration/soc_core: list rocket as supported CPU 2019-06-07 11:14:36 +02:00
Florent Kermarrec
ca4e7811e9 software/bios: change prompt to "litex" in green. 2019-06-07 11:13:36 +02:00
Florent Kermarrec
8d0f008a3b integration/soc_core: improve readibility (add separators/comments) 2019-06-05 23:43:16 +02:00
Florent Kermarrec
55ebcc00eb test/test_targets: add de10lite 2019-06-05 20:03:19 +02:00
enjoy-digital
e545b15f66
Merge pull request #196 from msloniewski/de10lite_support 
De10lite support
 2019-06-05 19:44:54 +02:00
enjoy-digital
77805a5e26
Merge pull request #195 from antmicro/extend_generated_headers 
Extend generated headers & csv
 2019-06-05 19:20:15 +02:00
msloniewski
04ce479035 boards/targets: add target for de10lite platform 2019-06-05 18:57:59 +02:00
msloniewski
f2a740d51d boards/platforms: add de10lite Terasic platform support 2019-06-05 18:57:59 +02:00
msloniewski
a826aacac0 build/altera: Add possibility to turn off generation of .rbf file 
For some FPGAs (e.g. MAX10) .rbf file cannot be generated.
Add possibility to turn off that feature for those chips.
 2019-06-05 18:57:59 +02:00
Mateusz Holenko
93b61a65bf integration/builder: generate flash_boot address to csv 2019-06-05 17:37:23 +02:00
Mateusz Holenko
d0b019b1f0 integration/builder: generate shadow_base address to mem.h and csv 2019-06-05 17:37:09 +02:00
enjoy-digital
cb2d4372e4
Merge pull request #193 from gsomlo/gls-memcpy-fix 
software/libbase: memcpy: simple, arch-width agnostic implementation
 2019-06-04 21:49:18 +02:00
Gabriel L. Somlo
f88b85a31c software/libbase: memcpy: simple, arch-width agnostic implementation 
Remove optimizations targeted specifically at rv32 architecture,
allowing memcpy to work on all word sizes.

Since this is "only" the BIOS, it is also arguably better to
optimize for size rather than performance, given that control
will be quickly handed over to some other program being loaded.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-06-04 14:48:51 -04:00
Tim Ansell
42e9d09755
Merge pull request #192 from sutajiokousagi/pr_c99_types 
fix signed char type to be explicitly signed
 2019-06-02 16:54:20 -07:00
bunnie
ab0b2cac2e fix signed char type to be explicitly signed 2019-06-03 06:01:13 +00:00
bunnie
200d413def update stdint.h to include c99 types 
needed for some third party libraries to compile
 2019-06-02 22:27:12 +00:00
Tim Ansell
b0d35a49f2
Merge pull request #191 from sergachev/master 
Fix interrupt_name in soc_core/add_interrupt
 2019-06-02 13:00:20 -07:00
Ilia Sergachev
db890736ea fix csr_name in add_csr() 2019-06-02 20:56:02 +02:00
Ilia Sergachev
40cbe3a952 fix interrupt_name 2019-06-02 20:52:31 +02:00
Florent Kermarrec
b300c32103 test/test_targets: add de2_115, de1soc 2019-06-02 19:22:09 +02:00
Florent Kermarrec
220e2bdc6e boards/platform/arty: add Arty A7-100 variant 2019-06-02 19:10:44 +02:00
enjoy-digital
8e6ecfb974
Merge pull request #189 from open-design/terasic-boards 
Add support for Terasic DE2-115 and Terasic DE1-SoC boards
 2019-06-02 18:40:57 +02:00
Tim Ansell
9682189b40
Merge pull request #190 from sutajiokousagi/pr_c99_types 
update stdint.h to include c99 types
 2019-06-02 08:15:52 -07:00
Antony Pavlov
6cf1a814eb boards: add Terasic DE2-115 initial support 
See https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=502&PartNo=1
for board details.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
 2019-06-02 11:33:10 +03:00
Antony Pavlov
037259917a boards: add Terasic DE1-SoC Board support 
See https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=836
for board details.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
 2019-06-02 11:26:21 +03:00
enjoy-digital
a48858f828
Merge pull request #188 from gsomlo/gls-csr-cleanup 
Miscellaneous cleanup patches
 2019-05-30 22:40:39 +02:00
Gabriel L. Somlo
273a3ea15d soc/integration/cpu_interface: improve code legibility 
Factor out code appearing in both branches of an if/else.
 2019-05-29 10:07:43 -04:00
Florent Kermarrec
08a811b1a5 soc/interconnect/gearbox: add msb_first/lsb_first order 2019-05-29 10:25:25 +02:00
Florent Kermarrec
675f78304e boards/targets/arty: generate 25MHz ethernet clock with S7PLL 
Allow ethernet to work when sys_clk_freq != 100MHz
 2019-05-28 09:55:06 +02:00
Tim Ansell
d7b00c8c4d
Merge pull request #187 from open-design/indent 
litex/boards/targets: don't use tab for indentation
 2019-05-26 03:01:31 -07:00
Antony Pavlov
26e6355fd6 litex/boards/targets: don't use tab for indentation 
Fix pep8 E101 "indentation contains mixed spaces and tab" error.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
 2019-05-26 12:00:03 +03:00
Florent Kermarrec
5109511259 soc/interconnect/axi: add round/robin arbitration between writes/reads 2019-05-25 10:02:31 +02:00
Florent Kermarrec
0fb6342f7b travis: update RISC-V toolchain 2019-05-25 09:30:54 +02:00
Florent Kermarrec
961101d809 bios/irc: remove compilation workaround 2019-05-25 09:24:48 +02:00
Florent Kermarrec
cd543b290c README: update RISC-V toolchain 2019-05-25 09:24:25 +02:00
Florent Kermarrec
7e837bf1d0 .gitmodules/rocket: switch to https://github.com/enjoy-digital/rocket-litex-verilog 2019-05-24 10:39:48 +02:00
Florent Kermarrec
712977a0cf software/bios/isr.c: workaround compilation issue (need to be fixed) 2019-05-24 10:18:50 +02:00
Florent Kermarrec
28ba8b3201 soc/integration/soc_core: revert default mem_map (do specific RocketChip remapping for now) 2019-05-24 10:18:32 +02:00
Florent Kermarrec
cf369c437c boards/targets: revert default sys_clk_freq on nexys4ddr/versa_ecp5 (but add parameter to configure it) 2019-05-24 10:18:26 +02:00
enjoy-digital
aa640f2999
Merge pull request #186 from gsomlo/gls-rocket 
Experimental Support for 64-bit RocketChip
 2019-05-24 10:15:02 +02:00
Gabriel L. Somlo
019fd94005 fixup: generated-verilog submodule for experimental Rocket support 
FIXME: This patch uses https://github.com/gsomlo/rocket-litex-verilog,
however in the long term it would perhaps be better if enjoy-digital
hosted the generated-verilog repository.
Once that's in place, I'd be happy to re-spin (and squash) this patch
on top of its parent -- GLS
 2019-05-23 18:22:37 -04:00
Gabriel L. Somlo
1a530cf27d soc/cores/cpu/rocket: Support for 64-bit RocketChip (experimental) 
Simulate a Rocket-based 64-bit LiteX SoC with the following command:

  litex/tools/litex_sim.py [--with-sdram] --cpu-type=rocket

NOTE: Synthesizes to FPGA and passes timing at 50MHz on nexys4ddr
(with vivado) and ecp5versa (with yosys/trellis/nextpnr), but at
this time does not yet properly initialize physical on-board DRAM.
On ecp5versa, using '--with-ethernet', up to 97% of the available
TRELLIS_SLICE capacity is utilized.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-05-23 15:59:51 -04:00
enjoy-digital
3de49118d9
Merge pull request #185 from gsomlo/gls-sim-sdram 
tools/litex_sim: restore functionality of '--with-sdram' option
 2019-05-23 15:52:33 +02:00
Gabriel L. Somlo
e90caa8683 tools/litex_sim: restore functionality of '--with-sdram' option 
After LiteDRAM commit #50e1d478, an additional positional argument
('databits') is required by the PhySettings() constructor.

The value used here (32) will generate a 64MByte simulated SDRAM.
 2019-05-23 08:56:50 -04:00
enjoy-digital
3a72688b28
Merge pull request #183 from xobs/usb-to-0x43 
Use 0x43/0xc3 for USB bridge magic packet
 2019-05-21 07:19:15 +02:00
Sean Cross
014c950580 remote: usb: print "access denied" error 
When we get an error with errno 13, it means that the user doesn't
have access to the USB device.  Rather than silently eating this
error and returning -1, print out a message to aid in debugging.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-05-21 09:36:18 +08:00
Sean Cross
faf6554c89 remote: usb: use 0x43/0xc3 for packet header 
The previous value -- 0xc0 -- is used by Windows all the time to query
special descriptors.  This was causing a conflict when using the USB
bridge on a Windows device.

Change the magic packet from "Vendor: Device" queries to "Vendor:
Other" by setting the bottom two bits.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-05-21 09:14:18 +08:00
Florent Kermarrec
10670e22ac soc/cores/minerva: update to latest 2019-05-17 22:21:57 +02:00
enjoy-digital
a3134f13b1
Merge pull request #182 from gsomlo/gls-nexys4-eth-fixup 
boards/nexys4ddr: ethernet support fix-up
 2019-05-17 16:33:34 +02:00
Gabriel L. Somlo
5707bdc0a4 boards/nexys4ddr: ethernet support fix-up 
Commit 5f6e7874 added ethernet support, let's now also expose it via
the "--with-ethernet" command line argument.
 2019-05-17 10:06:12 -04:00