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Author SHA1 Message Date
Dolu1990
07a8e696ce cpu/vexriscv_smp Add --with-coherent-dma 2020-08-06 13:33:11 +02:00
Florent Kermarrec
9a4c5aa1ef integration/soc/add_sdram: update rules to connect main bus to dram. 
Requires connection when CPU does not have memory buses of when CPU has memory buses
but no DMA bus.
 2020-08-05 18:01:12 +02:00
Florent Kermarrec
a1644510bf cpu/vexriscv_smp: fix args_read. 2020-08-05 17:59:30 +02:00
Florent Kermarrec
896b68cd6b cpu/vexriscv_smp: cleanup, fix coherent_dma connection. 2020-08-05 17:25:13 +02:00
enjoy-digital
342f359e1c
Merge pull request #622 from antmicro/fix_connectors 
arty: Change USB-uart and I2S Pmod configuration
 2020-08-05 12:30:34 +02:00
Florent Kermarrec
3b293612a8 soc/interconnect/axi: minor cleanups. 2020-08-05 12:11:28 +02:00
Florent Kermarrec
303d6cca7e interconnect/stream: set default AsyncFIFO depth to None and add depth parameter to ClockDomainCrossing. 2020-08-05 12:11:12 +02:00
Pawel Sagan
de9ea19cc7 arty: Change USB-uart and I2S Pmod configuration 
This makes it compatible with the Arty A7 expansion board by Antmicro
(https://github.com/antmicro/arty-expansion-board).
 2020-08-05 11:38:51 +02:00
Florent Kermarrec
00629c45b0 interconnect/csr: add CSR registers ordering support. 
The original CSR registers ordering (big: MSB on lower addresses) is not convenient
when the SoC is interfaced with a real OS (for example as a PCIe add-on board or
with a CPU running Linux).

With this, the original ordering is kept as default (big), but it can now be switched
to little to avoid software workarounds in drivers and should probably be in the future
the default for PCIe/Linux SoCs.
 2020-08-05 08:57:19 +02:00
Florent Kermarrec
ee7a7f4693 soc/interconnect/csr: improve ident. 2020-08-05 07:59:35 +02:00
Florent Kermarrec
b1008b0164 integration/soc: add expection on decoder when full address space is mapped. 2020-08-04 19:56:26 +02:00
Florent Kermarrec
b831dc8c55 wishbone: revert default adr_width to 30. 2020-08-04 19:55:46 +02:00
Florent Kermarrec
abc49964ea tools/litex_json2dts: add missing copyrights. 2020-08-04 16:38:02 +02:00
Florent Kermarrec
aed0dcee4c setup: add litex_json2dts to console_scripts. 2020-08-04 16:07:53 +02:00
enjoy-digital
b64209b38b
Merge pull request #620 from antmicro/add_litex_json2dts 
Add Linux DT generation script
 2020-08-04 16:04:57 +02:00
Florent Kermarrec
0ca99b798f build/sim/config: add default_clk/default_clk_freq parameters for retro-compatibility with previous API. 2020-08-04 15:49:53 +02:00
Florent Kermarrec
696ea468b8 build/sim: use json_object_get_int64 instead of json_object_get_uint64. 
json_object_get_uint64 does not seem supported with old json-c versions.
 2020-08-04 15:49:26 +02:00
enjoy-digital
382c1a3a44
Merge pull request #619 from antmicro/jboc/sim-clocker 
Allow to define multiple simulation clocks
 2020-08-04 15:38:28 +02:00
Mateusz Holenko
fafa844aa7 json2dts: Add Linux DT generation script 2020-08-04 15:13:17 +02:00
Jędrzej Boczar
f778ff09dc build/sim: improve timebase calculation (strict checks) and update modules 2020-08-04 14:00:58 +02:00
Florent Kermarrec
e0f131a317 cores/uart: add txempty/rxfull CSRs. 
Useful in some use cases, like flushing tx.
 2020-08-04 13:50:46 +02:00
Florent Kermarrec
2a3e39b10e tools/litex_server: enable read_merger with CommUDP. 
Limited to 4 (current size of the buffer in liteeth.frontend.etherbone).
 2020-08-04 10:55:51 +02:00
Florent Kermarrec
a5d0a340c3 test: specify wishbone adr_width on AXI(Lite)<-->Wishbone tests and remove debug traces. 2020-08-04 09:39:23 +02:00
enjoy-digital
eb3374d00a
Merge pull request #617 from gsomlo/gls_rocket_dma 
RFC: enable DMA with Rocket
 2020-08-04 09:38:58 +02:00
Gabriel Somlo
561331ed97 debug: make CI print offending values 2020-08-03 16:59:39 -04:00
Gabriel Somlo
df3428be07 liblitesdcard/sdcard: (temporarily) slow down SDCARD_CLK_FREQ to 25MHz 
Rocket's DMA slave interface (and/or internal routing) currently
appears unable to route DMA writes from LiteSDCard at frequencies
above 25MHz (as tested on nexys4ddr, with Rocket, at 75MHz main
system clock frequency).

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-08-03 16:14:11 -04:00
Gabriel Somlo
2d9dc8f939 cores/cpu/rocket: expose slave port for DMA 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-08-03 16:14:11 -04:00
Gabriel Somlo
d8161e5a86 integration/soc: make DMA slave region cover (at least) the lower 4GB 
Assuming we currently support a 32-bit (4GB) physical address space,
ensure that the dma_bus slave covers the entire range, covering any
possible layout of the LiteX SoC memory map (e.g., rocket has MMIO
in a wide range of registers located below 2GB, and DRAM starting at
the 2GB mark, needing DMA accesses to be routed appropriately for the
entire 4GB physical address range).

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-08-03 16:14:11 -04:00
Gabriel Somlo
70eae5cbf9 interconnect/wishbone: increase WB address width to 31 
This is needed to support memory regions up to 4GB in size (currently
limited to 2GB, or 0x8000_0000).

FIXME: CI complains about assertions re. axi_lite.address_width in
       relationship to len(wishbone.adr) and wishbone_adr_shift, which
       seems to be a problem on the 32bit (vexriscv?) CPU used for CI,
       but seems to work fine on Rocket.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>

foo
 2020-08-03 16:11:26 -04:00
Gabriel Somlo
b8c9da81ea soc/interconnect/axi: add Wishbone2AXI converter 2020-08-03 12:50:00 -04:00
Florent Kermarrec
2ec4604c41 cores/gpio: add support for Record on GPIOOut, GPIOIn and GPIOInOut. 2020-08-03 18:47:17 +02:00
Jędrzej Boczar
c1ae7e596c build/sim: allow for arbitrary clocks generation using clockers 2020-08-03 17:06:38 +02:00
Jędrzej Boczar
38054874ac build/sim: use a real timebase in the simulation 2020-08-03 15:21:24 +02:00
enjoy-digital
5e53e5d73a
Merge pull request #615 from pepijndevos/openfpgaloader 
Add openFPGALoader programmer
 2020-08-03 14:01:50 +02:00
Pepijn de Vos
79ca4d9640 remove debugging 2020-08-01 11:07:04 +02:00
Pepijn de Vos
f6e20700d4 add openFPGAloader programmer 2020-08-01 11:05:09 +02:00
Florent Kermarrec
eab0726cc8 cpu/vexriscv/core: use variant name as human_name. 
Allow it to be shown in the BIOS and help support.
 2020-07-31 08:59:53 +02:00
Florent Kermarrec
e0a763e534 cpu/vexriscv/system.h: provide empty flush_cpu_i/dcache functions for variants with no i/d cache. 2020-07-31 08:58:30 +02:00
Florent Kermarrec
3ff1bcaf05 cpu/zynq7000: set csr map to 0x00000000. 2020-07-30 21:37:25 +02:00
enjoy-digital
c0253e3f77
Merge pull request #611 from antmicro/jboc/axi-lite 
soc/interconnect/axi: add AXILite -> AXI converter
 2020-07-30 14:22:21 +02:00
Florent Kermarrec
cc8440549f tools/litex_server/read_merger: review/simplify a bit. 2020-07-30 13:58:40 +02:00
enjoy-digital
4f382ccf55
Merge pull request #605 from cklarhorst/feature-uart-read-merger 
Merge sequential reads for the UART litex_server backend
 2020-07-30 13:56:48 +02:00
Jędrzej Boczar
e78d950a31 soc/interconnect/axi: add AXILite -> AXI converter 2020-07-30 13:50:34 +02:00
Florent Kermarrec
a942e358b9 cpu/blackparrot: minor cleanups, add sim variant (since use different flist). 2020-07-30 12:10:32 +02:00
enjoy-digital
86e910dfaa
Merge pull request #610 from Dolu1990/vexriscv_smp 
soc/cores/cpu/vexriscv_smp enable dynamic litedram datawidth
 2020-07-29 18:11:00 +02:00
Dolu1990
023ab15ec1 soc/cores/cpu/vexriscv_smp enable dynamic litedram datawidth 2020-07-29 12:40:16 +02:00
Dolu1990
e5cd5d5466 Merge branch 'master' into vexriscv_smp 2020-07-29 11:14:09 +02:00
Florent Kermarrec
1938ce363d integration/soc/add_sdram: allow the CPU to add the direct memory buses when adding the sdram. 
This is useful for CPUs elaborated at buildtime to use sdram's native data width on the CPU memory ports.
 2020-07-29 11:10:05 +02:00
Florent Kermarrec
6576416b8e cores/cpu/rocket: add use_memory_bus parameter to easily disable direct memory bus for testing. 
Useful for current tests with LiteSDCard using DMA and that requires the DMA to be connnected to
the DMA bus of Rocket when the direct memory bus is used.
 2020-07-29 09:35:15 +02:00
Dolu1990
789a70e7c8 Merge branch 'master' into vexriscv_smp 2020-07-28 19:11:54 +02:00