0c1f0b17b4
integration/soc_core: Create soc parser group to improve --help readibility.
2022-01-05 18:30:04 +01:00
ec75228a72
builder: Create builder parser group to improve --help readibility.
2022-01-05 18:29:38 +01:00
67fa433efa
tools: Switch most the tools to argparse.ArgumentDefaultsHelpFormatter and uniformize help style.
2022-01-05 16:04:31 +01:00
54a137ef9f
builder: Use argparse.ArgumentDefaultHelpFormatter to automatically show default in help.
2022-01-05 16:03:38 +01:00
6f3f695d61
tools/litex_sim: Minor cleanups.
2022-01-05 15:20:27 +01:00
c424e51df4
litex_setup: Improve script status prints.
2022-01-05 14:52:21 +01:00
a6e2a529dc
litex_setup: Add initial installs config support (minimal, standard, full).
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Can be selected with --config=minimal/standard/full. This avoid installing all the
CPUs when only the popular ones will be used. Installation can be updated later
and switched to full installation with --config=full.
2022-01-05 13:56:35 +01:00
04e73b2e33
litex_setup.py: Switch git clone to git@github.com URLs when in --dev mode.
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Simplify dev/maintenance.
2022-01-05 10:07:35 +01:00
ba79224939
Bump year.
2022-01-05 09:21:08 +01:00
3fde251216
CHANGES: Set release date.
2022-01-05 08:53:10 +01:00
e21044641e
cores/cpu/vexriscv_smp: Force wishbone_memory mode when no direct memory_buses.
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This ensures a path for memory accesses will be created LiteDRAM is not used (ex with an HyperRAM memory).
2022-01-04 15:16:31 +01:00
f04a3dcc50
CHANGES: List changes since 2021.08.
2022-01-03 19:29:05 +01:00
c6dff1ea7e
Merge pull request #1141 from sergachev/zynq7000_bios
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Zynq7000 ARM BIOS support
2022-01-03 17:57:40 +01:00
3b05fa57d4
Merge pull request #1140 from sergachev/cleanup_defaults
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argparse: deduplicate defaults in help messages
2022-01-03 14:59:19 +01:00
79d0f0a893
interconnect/wishbone/axi: Automatically get InterconnectShared's shared data_width from first master.
2022-01-03 14:53:06 +01:00
90c204e87f
Merge pull request #1148 from tongchen126/master
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soc/software/bios/cmds/cmd_mem.c: fix number of required params
2022-01-03 14:40:39 +01:00
a8c8e4e3cf
litex/soc/interconnect/wishbone.py: add data_width param
2021-12-31 13:27:27 +08:00
e87e7ff31c
soc/software/bios/cmds/cmd_mem.c: fix number of required params
2021-12-30 20:43:05 +08:00
8ac3fbc039
soc/cores/led: Split LED-SHIFT in LED-READ/LED-SHIFT, simplify and fix off by one error.
2021-12-27 14:06:04 +01:00
2c68135eb4
Merge pull request #1143 from enjoy-digital/Dolu1990-patch-1
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tools/litex_json2dts_linux.py fix double {{
2021-12-27 12:34:19 +01:00
f4967cfb85
tools/litex_json2dts_linux.py fix double {{
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A string with a {{ was missing the .format call, generating some broken dts
2021-12-26 12:17:33 +01:00
6b207f876b
software/bios: add separate linker file for zynq
2021-12-22 03:01:25 +01:00
d75dd653bc
integration/soc: unblacklist zynq
2021-12-22 03:01:06 +01:00
0c57021c3c
software: add minimal xilinx library makefile
2021-12-22 03:00:05 +01:00
6705972713
builder: enable bios compilation on zynq
2021-12-22 02:59:40 +01:00
76148c4930
zynq: add minimal software compilation support
2021-12-22 02:58:33 +01:00
4f39faf737
software/libc: enable compilation on arm
2021-12-22 02:57:52 +01:00
94f4dd78f2
zynq: update gcc triple, set fpu flags
2021-12-22 02:57:07 +01:00
a07a4e0e86
zynq: cleanup
2021-12-22 02:56:46 +01:00
68e40dd330
zynq: remove broken unused method
2021-12-22 02:56:21 +01:00
b7f787a461
software: disable exceptions on arm cpus (problems compiling)
2021-12-22 02:55:33 +01:00
5357d66c93
software/libc: fix missing return
2021-12-22 02:54:32 +01:00
4c20501218
software/libcompiler_rt: enable missing math operations on arm
2021-12-22 02:54:19 +01:00
490929ab65
software/libcompiler_rt: cleanup flags
2021-12-22 02:53:58 +01:00
893044275e
software/libc: remove fexceptions flag already present in common.mak
2021-12-22 02:53:24 +01:00
ab8c509396
argparse: deduplicate defaults in help messages
2021-12-22 02:45:58 +01:00
d36e1b60bd
Merge pull request #1139 from tilk/jtagbone_typo
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Fix typo jtabone -> jtagbone
2021-12-21 19:22:01 +01:00
92c8f7dc7c
Fix typo jtabone -> jtagbone
2021-12-21 18:10:12 +01:00
72126f90a0
Merge pull request #1138 from fjullien/efinix_add_ifacewriter_mipi_clkin
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efinix: add gpio MIPI_CLKIN to ifacewriter
2021-12-21 15:34:51 +01:00
1a9716048f
Merge pull request #1136 from antmicro/fix-regions-filter
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tools/litex_json2renode: Add more restrictions to memory regions filter
2021-12-21 15:34:25 +01:00
2174a9219b
efinix: add gpio MIPI_CLKIN to ifacewriter
2021-12-21 12:39:22 +01:00
55268af279
Merge pull request #1129 from gsomlo/gls-json2dts-update
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clock, mmc updates for json2dts_linux
2021-12-20 21:27:06 +01:00
9e44e856cc
Merge pull request #1137 from trabucayre/zynq_tcl_preset
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zynq7000: add TCL preset support
2021-12-20 21:25:40 +01:00
58f9bce567
Merge pull request #1135 from fjullien/bios_add_variable_size_mem_write
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bios: add write size option to cmd mem_write
2021-12-20 21:23:16 +01:00
14e0aeb92a
zynq7000: add TCL preset support
2021-12-20 16:54:18 +01:00
bf52f222af
tools/litex_json2renode: Add more restrictions to memory regions filter
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Skip regions that have size==0 or if region is included in another region.
Abort script if region overlap on another region.
Signed-off-by: Robert Szczepanski <rszczepanski@antmicro.com>
2021-12-20 13:56:40 +01:00
f4dab5adac
bios: add write size option to cmd mem_write
2021-12-17 20:45:41 +01:00
321b91d551
Merge pull request #1134 from fjullien/efinix_titanium_support
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Efinix titanium support
2021-12-17 15:55:08 +01:00
ca67ed8c13
efinix: check SLEWRATE property when adding a 'normal' GPIO
2021-12-17 13:52:05 +01:00
df20ea5aa8
efinix: when a GPIO block is added, also add pin properties
2021-12-17 13:52:05 +01:00
Florent Kermarrec
tongchen126
Dolu1990
Ilia Sergachev
Marek Materzok
Franck Jullien
Gwenhael Goavec-Merou
Robert Szczepanski