e12187aa80
add += operator to fragment
2013-08-12 13:15:05 +02:00
fdf022a04b
fhdl: improve naming of related signals
2013-08-08 19:22:17 +02:00
2c580fff03
fhdl/namer: detect leaf nodes better
2013-08-08 12:22:58 +02:00
eb1417c5ed
fhdl: move insert_resets to tools
2013-08-08 11:32:58 +02:00
305c6985bc
fhdl: support for naming related signals
2013-08-08 11:32:37 +02:00
146a1b5d51
namer: add HUID suffix step
2013-08-08 00:15:18 +02:00
fd34b75fb4
namer: split by numbers
2013-08-07 23:22:40 +02:00
0e369318bb
treeviz: support multiline labels
2013-08-07 21:46:03 +02:00
ceddd8afa4
treeviz: improve layout of unbalanced trees
2013-08-07 18:32:02 +02:00
7a243171bd
fhdl/namer: new namer with explicit tree
2013-08-07 17:13:52 +02:00
cc5ff7a772
add tree visualizer
2013-08-07 15:52:35 +02:00
efa7dc9cf4
fhdl/edif: adjust for use with mibuild
2013-08-03 10:54:06 +02:00
7372c7a97c
fhdl/edif: add support for inout signals
2013-08-03 10:51:24 +02:00
0e195da3c0
bank/csrgen: add get_offset function to pre-calculate register addresses
2013-08-02 23:05:54 +02:00
2a296aced7
bank/description/AutoCSR: prefix csr/mem only once
2013-08-02 23:05:21 +02:00
17002fb05e
fhdl: add EDIF back-end
2013-07-31 22:47:43 +02:00
246b860a85
csr: new data width API
2013-07-28 16:33:36 +02:00
6ba0d4bd0d
bus/wishbone: configurable data width
2013-07-27 22:25:07 +02:00
14ed5c1acc
genlib/record: support abstract signal width
2013-07-27 22:18:06 +02:00
7e20320b9d
pytholite/io: len -> flen
2013-07-27 15:38:48 +02:00
04ec60541c
pythloite/ExprCompiler: attempt compile-time evaluation first
2013-07-27 15:38:29 +02:00
f62eff0309
bus/csr/Initiator: correct read latency
2013-07-27 15:37:47 +02:00
e05f520cdf
actorlib/spi: remove unused function
2013-07-27 15:36:42 +02:00
61b8958953
fix synthesis translate on/off switch
2013-07-26 15:55:16 +02:00
9c7ad6b05b
fhdl: RenameClockDomains decorator
2013-07-26 15:42:14 +02:00
cec8fc4ca4
fhdl/specials/Instance: fix item sorting
2013-07-26 14:00:29 +02:00
6e1195415e
genlib/roundrobin: fix n==1 case (correctly)
2013-07-26 09:33:33 +02:00
b8ff2f2792
genlib/roundrobin.py: fix n==1 case
2013-07-26 00:41:08 +02:00
b96eb339af
fhdl: compact Instance syntax
2013-07-25 20:34:19 +02:00
b7ed19c6c5
fhdl: do not export Fragment
2013-07-25 18:52:54 +02:00
b367932498
fhdl: introduce module decorators
2013-07-25 17:56:31 +02:00
cabae0c32b
genlib: remove direct uses of Fragment
2013-07-24 19:25:14 +02:00
fe18397acc
wishbone.py: add Crossbar (concurrent/parallel/many-to-many interconnect)
2013-07-22 10:30:44 +02:00
5bc9a0b383
fsm.py: set reset_state
2013-07-22 10:30:40 +02:00
411e6ec114
fhdl/tools: do not export resort_statements
2013-07-17 16:50:09 +02:00
d5d2e64dc3
Revert "fhdl/tools/group_by_target: remove resort_statements"
...
This reverts commit 939f01cee2
2013-07-17 16:49:26 +02:00
9190568685
genlib/fifo/AsyncFIFO: fix data corruption bug
2013-07-17 12:10:39 +02:00
939f01cee2
fhdl/tools/group_by_target: remove resort_statements
2013-07-17 10:38:39 +02:00
16ebe41028
fhdl/tools: BUGFIX: fix group_by_target grouping
...
group_by_target does not properly combine target groups if statements
are presented in the order:
({A}, statement1)
({B}, statement2)
({A, B}, statement3)
which returns groups:
({A, B}, [statement1, statement3])
({B}, [statement2])
This patch fixes group_by_target such that the resulting group is:
({A, B}, [statement1, statement2, statement3])
2013-07-17 10:14:39 +02:00
5b36f688ea
Remove ASMI
2013-07-16 18:50:50 +02:00
faa8b7c49a
fhdl/tools: clock domain merging for clock renaming
2013-07-16 18:17:44 +02:00
b016a60b85
lasmibus: fix master locking
2013-07-15 21:45:07 +02:00
7083764b53
genlib/fifo: add test bench
2013-07-15 21:36:39 +02:00
65a0b12812
actorlib/spi/DMAController: export length/storage/trigger
2013-07-13 17:13:15 +02:00
6595b9a111
actorlib/spi/SingleGenerator: export CSRs
2013-07-13 17:12:51 +02:00
c2d6f14087
flow/actor/PipelinedActor: clean up
2013-07-12 18:52:34 +02:00
6aa1e0c199
actorlib/spi/DMAWriteController: len -> flen
2013-07-11 19:22:56 +02:00
f5ddd33e7e
dfi: split phase description
2013-07-10 19:56:47 +02:00
43fe16ef73
bus/lasmibus: add separate req/data ack to target and initiator
2013-07-10 19:09:51 +02:00
af6ef0a3b4
dma_lasmi/Writer: fix default FIFO depth
2013-07-07 20:01:55 +02:00
Nina Engelhardt
Sebastien Bourdeauducq
Nina Engelhardt
Robert Jordens
David Carne
Florent Kermarrec