e42ab27f30
gen/fhdl/verilog: revert _printcomb_simulation and _printcomb_regular (needed for icarus simulation) and add Finish command
2017-09-13 13:47:25 +02:00
2a8f6edded
soc/integration/soc_core: add ident_version parameter to allow adding soc version to identifier
2017-09-06 15:39:54 +02:00
797a91270f
Merge pull request #27 from enjoy-digital/etherbone-docs
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Adding a little docs to field descriptions.
2017-09-01 15:54:38 +02:00
c125ea6440
Adding a little docs to field descriptions.
2017-09-01 23:27:58 +10:00
8f3dcf90ab
soc/software/bios/sdram: add optional memtest debug traces
2017-08-18 09:42:27 +02:00
c02de1632b
soc/cores: fix vivado issue with SPIRegister (at least with Vivado 2017.x+, mosi was not generated correctly), create cs_n signal if pads does not exists
2017-07-27 18:22:01 +02:00
04646b24ed
soc/interconnect/stream: fix make_m2s for reset_less
2017-07-24 18:18:35 +02:00
9509d9e361
gen/genlib/cdc/gearbox: fix possible pointers overlap by removing AsyncResetSynchronizers.
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read/write clocks don't have the same frequencies, using AsyncResetSynchronizers cause differents delay when releasing reset and can cause pointers overlap.
2017-07-24 13:39:08 +02:00
f25e46c428
Merge pull request #26 from q3k/diamond-linux-support
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Add Diamond toolchain support for Linux.
2017-07-20 14:41:05 +02:00
503df5e93e
Add Diamond toolchain support for Linux.
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This tries to replicate the same setup as in the Windows buildsystem. We
also remove the Jedecgen step, as it doesn't seem to be supported nor
necessary in newer versions of Diamond.
2017-07-20 13:21:10 +01:00
756554371a
soc/tools/remote/litex_server: allow multiple instance of server
2017-07-19 21:18:12 +02:00
0b6d38abe9
build/xilinx/programmer: add multi jtag devices support to VivadoProgrammer
2017-07-19 14:54:19 +02:00
d05d170b75
soc/integration/cpu_interface: do not generate constant access functions when with_access_functions is set to False
2017-07-19 12:18:35 +02:00
20c859d45c
soc/tools/remote/etherbone: speed optimization (~20/30%)
2017-07-17 00:25:58 +02:00
bdea4152e3
soc/core/uart: add UartStub to enable fast simulation with cpu
2017-07-06 19:19:10 +02:00
734ecead36
Merge pull request #25 from q3k/master
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Add Versa ECP5-5G Platform.
2017-07-05 16:22:50 +02:00
1885e50d54
Add Versa ECP5-5G Platform.
2017-07-05 15:01:07 +01:00
0894f9e6f7
targets: cleanup arty/nexys_video/kc705 and use better ddr3 timings on arty/nexys_video (found using the new bitslip/delay finder tool)
2017-07-04 09:01:29 +02:00
fe535db5ab
merge migen ee0e709 changes
2017-07-04 08:15:40 +02:00
c6f6d7b491
soc/interconnect/wishbonebridge: reset_less optimizations
2017-06-30 19:41:14 +02:00
7fcdd94cd4
soc/interconnect/stream_packet: reset_less optimizations
2017-06-30 19:40:54 +02:00
227b14c3f3
soc/interconnect/stream: improve reset_less support for streams
2017-06-30 19:40:17 +02:00
f5a971a8d8
soc/interconnect/stream: use reset_less attr of signal for payload and param
2017-06-28 23:10:45 +02:00
bd876d4cd6
merge migen 9a6fdea3 changes
2017-06-28 22:47:13 +02:00
4d664730fe
soc/software/libbase: fix get_ident
2017-06-28 18:10:56 +02:00
e61d9eabc6
board/targets/sim: add identifier
2017-06-28 18:08:37 +02:00
4433e2449a
litex/build/sim: cleanup modules
2017-06-28 18:01:04 +02:00
c3710ec139
build/sim: cleanup serial2console and fix terminal mode
2017-06-28 17:38:09 +02:00
ebded4a1b9
README: add required packages for litex sim
2017-06-28 16:56:05 +02:00
5ece895fd3
litex/build/sim: add README
2017-06-28 16:55:32 +02:00
4a0a431119
litex/build/sim: rename c functions from lambdasim to litex_sim (since integrated in litex)
2017-06-28 16:28:45 +02:00
ab6f4de521
litex/build/sim: small cleanup
2017-06-28 16:25:56 +02:00
1d8298af94
litex/build/sim: add tapcfg submodule for ethernet
2017-06-28 16:18:15 +02:00
8510b12e93
litex/build/sim: introduce new simulator with modules support (thanks lambdaconcept)
2017-06-28 16:14:13 +02:00
6631aa5385
boards/platforms/arty: add pmods
2017-06-23 10:50:37 +02:00
1364ac3657
soc/cores/identifier: append 0 to contents to indicate end of string
2017-06-22 17:53:19 +02:00
bdc61106d1
README: consistency between projects
2017-06-22 17:01:13 +02:00
f720ef5631
soc/tools: simplify litex_server usage and integrage udp, pcie
2017-06-22 11:30:33 +02:00
41a91829eb
soc/tools: syntax fix on comm_pcie, import in __init__.py
2017-06-22 11:29:57 +02:00
c82c1d103f
soc/tools: fix debug prints of comm_pcie
2017-06-22 10:33:08 +02:00
684ae45dbe
soc/tools: remove csr builder from comm_udp (we should use litex_server)
2017-06-22 10:32:39 +02:00
4ea7026747
gen/fhdl/specials: revert migen's commit d98502c6 (specials/Memory: homogenize read-only port syntax) since causing a regression with litepcie
2017-06-10 21:53:53 +02:00
c44a4b051f
soc/interconnect/stream: add first signal to streams (avoid over-complicated code in some cases)
2017-06-09 19:35:48 +02:00
c19c4b711b
soc/cores/identifier: remove additionnal first character
2017-06-08 14:15:27 +02:00
77732fca95
soc/cores/uart: add uart multiplexer
2017-06-05 19:36:30 +02:00
157c2b17bc
boards/platforms/nexys_video: rename hpa to hdp_en on nexy_video hdmi_in port
2017-06-05 15:13:21 +02:00
a36986a501
gen/fhdl/verilog: list available clock domains on keyerror
2017-06-05 14:33:46 +02:00
931ea5ac75
gen/genlib/cdc/gearbox: remove TODO since code is already a good compromise
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latency can't be reduced that much and reducing ressource usage (already low) would introduce unneeded complexity.
2017-06-01 19:00:22 +02:00
85aea62d74
soc/core: add frequency meter
2017-06-01 00:39:19 +02:00
ff2a9c2176
gen/genlib/cdc/gearbox: add more margin on pointers (for cases where clocks are not perfectly aligned)
2017-05-31 13:23:31 +02:00
Florent Kermarrec
Tim Ansell
Sergiusz Bazanski
Pierre-Olivier Vauboin