Florent Kermarrec
|
1c381acc6f
|
k7ddrphy: fix read_latency (CL is 2 sys_clk since we use quarter rate)
|
2014-08-14 22:46:06 +08:00 |
|
Florent Kermarrec
|
acbba37f5f
|
k7ddrphy: set bitslip to 0 on ISERDESE2 (needed at least for sim)
|
2014-08-14 22:46:06 +08:00 |
|
Florent Kermarrec
|
2e4bfe154f
|
k7ddrphy: add ODELAYE2 on dm path to match dq path (ODELAYE2 even configure with a delay of 0 generates a delay)
|
2014-08-14 22:46:06 +08:00 |
|
Florent Kermarrec
|
bb85f29f91
|
k7ddrphy: fix write_latency and take care of OSERDESE2 latency on oe
|
2014-08-14 22:46:06 +08:00 |
|
Florent Kermarrec
|
85b29c883a
|
sdramphy/initsequence: fix and add format_mr0 function
|
2014-08-14 14:17:54 +08:00 |
|
Florent Kermarrec
|
9844c25df9
|
k7ddrphy: add SERDES reset
|
2014-08-14 14:16:41 +08:00 |
|
Florent Kermarrec
|
194a5a0491
|
lasmicon: fix reset_n level
|
2014-08-14 14:15:48 +08:00 |
Sebastien Bourdeauducq
|
3a960e9e6a
|
flash_extra: use new programmer
|
2014-08-09 14:39:38 +08:00 |
|
Sebastien Bourdeauducq
|
a6c55d8dde
|
make.py: do not use prog.needs_flash_proxy
|
2014-08-09 14:38:56 +08:00 |
|
Sebastien Bourdeauducq
|
4d2623a87e
|
mor1kx: sync
|
2014-08-09 14:32:57 +08:00 |
|
Sebastien Bourdeauducq
|
c8dd4d2b40
|
k7ddrphy: send rddata_valid on all phases
|
2014-08-09 11:00:13 +08:00 |
|
Sebastien Bourdeauducq
|
41c8c172b5
|
targets/kc705: integrate DDR3
|
2014-08-08 21:58:41 +08:00 |
|
Sebastien Bourdeauducq
|
0ebdf2be6d
|
bios/sdram: cleanup
|
2014-08-08 21:57:58 +08:00 |
|
Sebastien Bourdeauducq
|
b61dced909
|
bios/sdram: set ODT and RESET_N through DFII
|
2014-08-08 21:57:42 +08:00 |
|
Sebastien Bourdeauducq
|
8deadc5760
|
dfii: drive ODT and RESET_N
|
2014-08-08 21:56:35 +08:00 |
|
Sebastien Bourdeauducq
|
1322c0484b
|
lasmicon: drive ODT and RESET_N
|
2014-08-08 21:55:34 +08:00 |
|
Sebastien Bourdeauducq
|
0550cbb3ce
|
lasmicon: add CWL to PHY settings
|
2014-08-08 21:55:12 +08:00 |
|
Sebastien Bourdeauducq
|
777ebb7875
|
sdramphy/gensdrphy: fix rddata_en generation
|
2014-08-08 21:41:07 +08:00 |
|
Sebastien Bourdeauducq
|
a2c7ff4c0c
|
sdramphy: initial K7 DDR3 support
|
2014-08-08 21:28:26 +08:00 |
|
Florent Kermarrec
|
293ac09673
|
sdramphy/bios: make sdrrd/sdrwr generic
|
2014-08-08 19:25:10 +08:00 |
|
Sebastien Bourdeauducq
|
cfc37a3fa5
|
sdramphy/initsequence: rewrite DDR3 initialization sequence
|
2014-08-08 19:15:05 +08:00 |
|
Sebastien Bourdeauducq
|
e8db842538
|
s6ddrphy: fix DFI interface data width computation
|
2014-08-08 19:14:15 +08:00 |
|
Sebastien Bourdeauducq
|
efb2466c7e
|
gensoc: add id for KC705
|
2014-08-06 23:53:51 +08:00 |
|
Sebastien Bourdeauducq
|
fb48b89bac
|
platforms/kc705: generate clocks for SDRAM
|
2014-08-06 23:53:26 +08:00 |
|
Sebastien Bourdeauducq
|
ca6d6954c1
|
targets/ppro: use migen reset synchronizer
|
2014-08-06 19:38:11 +08:00 |
|
Florent Kermarrec
|
d1ff43faa7
|
gensoc/cpuif: do not generate access functions for registers > 64 bits
|
2014-08-04 22:38:19 +08:00 |
|
Florent Kermarrec
|
452a4a76f3
|
use verilog namespace to export mila configuration
|
2014-08-03 17:09:01 +02:00 |
|
Sebastien Bourdeauducq
|
37968e649b
|
targets/kc705: use PLL for clocking
|
2014-08-03 21:42:39 +08:00 |
|
Florent Kermarrec
|
6ffed70b59
|
uart2wishbone: disconnect rx line from shared pads when bridge is selected
(avoid CPU crash when we communicate with the bridge)
|
2014-08-03 13:15:56 +02:00 |
|
Florent Kermarrec
|
f4e6cebab2
|
clean up
|
2014-08-03 11:44:27 +02:00 |
|
Sebastien Bourdeauducq
|
1a09eb7a19
|
mor1kx: sync
|
2014-08-03 15:57:55 +08:00 |
|
Sebastien Bourdeauducq
|
61eae462f3
|
README: update
|
2014-08-03 15:48:55 +08:00 |
|
Sebastien Bourdeauducq
|
f7a7137127
|
targets: add basic KC705
|
2014-08-03 15:48:30 +08:00 |
|
Sebastien Bourdeauducq
|
213cb43ae5
|
Keep only basic SoC designs in MiSoC
|
2014-08-03 12:30:15 +08:00 |
|
Florent Kermarrec
|
cd51e78f54
|
storage: use SyncFIFOBuffered to implement fifo in block ram
|
2014-08-02 19:12:03 +02:00 |
|
Florent Kermarrec
|
47a85cc1ad
|
use new MiSoC fifo (no flush signal)
|
2014-08-01 10:36:15 +02:00 |
|
Sebastien Bourdeauducq
|
9395214d75
|
remove stale programmer.py
|
2014-08-01 12:34:38 +08:00 |
|
Florent Kermarrec
|
62c9043d07
|
move programmer to mibuild
|
2014-08-01 08:03:53 +08:00 |
|
Florent Kermarrec
|
25b3aff6f1
|
sdramphy: add init sequence for DDR3
|
2014-07-31 10:29:32 +08:00 |
Yann Sionneau
|
32171da46d
|
Better UART baudrate generator, and testbench
This enables high speed (tested to 4Mbps) operation.
|
2014-07-31 10:24:52 +08:00 |
|
Sebastien Bourdeauducq
|
2cb7d73870
|
mor1kx: sync
|
2014-07-28 21:36:00 -06:00 |
|
Sebastien Bourdeauducq
|
8349543732
|
style
|
2014-07-05 18:56:20 +02:00 |
|
Sebastien Bourdeauducq
|
2bb821c571
|
crt-or1k: trim useless exception vectors
|
2014-07-05 18:53:23 +02:00 |
|
Sebastien Bourdeauducq
|
9a64309fcd
|
Merge branch 'master' of github.com:m-labs/misoc
|
2014-07-04 10:29:53 +02:00 |
|
Sebastien Bourdeauducq
|
6462ee7fe1
|
Upgrade mor1kx. This fixes the UART bug that was due to IRQ 0 and 1 being non-maskable.
|
2014-07-04 10:29:42 +02:00 |
|
Florent Kermarrec
|
d4833cb3dc
|
cpuif: remove limitations on csr data_width
|
2014-06-28 17:39:55 +02:00 |
|
Florent Kermarrec
|
a0df5baa55
|
host: add support for various csr_data width (8 & 32 tested, but should work with others)
|
2014-06-26 13:22:21 +02:00 |
|
Florent Kermarrec
|
0f9bc5ad6e
|
fix bit inversion on CSV/PY exports
|
2014-06-21 19:06:47 +02:00 |
|
Florent Kermarrec
|
074a12b444
|
create dump class and specific export functions, add python dictionnary export
|
2014-06-19 13:24:47 +02:00 |
|
Florent Kermarrec
|
a737358919
|
host: split read/export and add csv export
|
2014-06-17 11:25:10 +02:00 |