67cf67034c
cpus: remove common cpu variants/extensions definition and simplify variant check.
...
Having common cpu variants/extensions has no real additional value since we are supporting
very various CPUs where minimal/standard/full have different meanings. Checking against
common variants/extensions has also cause more issues recently when adding new CPUs than
the additional value it was supported to provide.
So let's just simplify things: a CPU provide the supported variants and we just check
against that.
2020-05-26 09:36:44 +02:00
062ff67e12
cpu/microwatt: add standard+ghdl variant that uses GHDL Yosys plugin.
2020-05-26 08:51:33 +02:00
24687cbd9f
tools/litex_client/RemoteClient: add base_address parameter.
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Useful when address translation is done in the SoC.
2020-05-25 14:11:14 +02:00
78a9579e09
cores/uart/RS232PHYTX: fix startbit duration by pre-loading phase_accumulator_tx to tuning_word.
2020-05-25 10:46:53 +02:00
370e46529d
Merge pull request #539 from dayjaby/pr-fix_uart_startbit
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Fix UART startbit: 1 cycle later
2020-05-25 10:33:58 +02:00
c75cf45ab4
tools: add litex_jtag_uart to create a virtual uart for the jtag uart.
2020-05-25 10:21:06 +02:00
2cf83b9f69
tools: rename litex_crossover poc to litex_crossover_uart, remove from setup for now.
2020-05-25 10:19:16 +02:00
e853ad4b61
fix uart startbit: 1 cycle later
2020-05-24 16:12:07 +02:00
bed5aafd6c
tools: add litex_crossover to be able to use lxterm (and serialboot) over a crossover UART (bridged over UART/Ethernet/PCIe/USB, etc...).
...
This is still a proof of concept but can be used/tested with:
lxsim --with-etherbone --uart-name=crossover --csr-csv=csr.csv
lxserver --udp --udp-ip=192.168.1.51
lxcrossover (will indicate the virtual_tty)
lxterm virtual_tty
2020-05-24 10:55:25 +02:00
3833bc3ec3
litex_sim: override uart_name to sim only for serial.
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Using uart_name=crossover is useful to simulate crossover mode.
2020-05-24 09:52:56 +02:00
da7fd30847
CHANGES: update.
2020-05-23 18:56:51 +02:00
2fb52e66b1
integration/soc: remove TODO in header.
2020-05-23 18:54:04 +02:00
b65f18c357
cpu/cv32e40p: fix copyright year.
2020-05-23 18:53:03 +02:00
30f3517041
cpu/cv32e40p: add copyright and improve indentation.
2020-05-22 15:55:35 +02:00
b23702ecc4
litex_setup/pythondata-cpu-cv32e40p: clone in recursive mode.
2020-05-22 15:43:00 +02:00
4c4cd335de
Merge pull request #535 from antmicro/arty-cv32e40p
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Add support for the CV32E40P RISC-V CPU
2020-05-22 13:44:10 +02:00
7d09ea19ef
Merge pull request #538 from antmicro/fix_libbase
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libbase: Include missing uart header
2020-05-22 12:28:00 +02:00
9d16b0fc82
libbase: Include missing uart header
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This fixes compilation on mor1kx.
2020-05-22 11:43:18 +02:00
3d06dc028c
test/test_targets: update build_test.
2020-05-22 08:42:02 +02:00
bdc7eb5c48
litex_sim: load SPD data from files in hexdump format as printed in BIOS
2020-05-21 16:20:06 +02:00
a42dc97401
bios/sdram: add BIOS command for reading SPD
2020-05-21 14:32:31 +02:00
8fd3e74ec9
bios/sdram: add firmware for reading SPD EEPROM
2020-05-21 14:07:42 +02:00
42350f6d83
platforms/targets: keep in sync with litex-boards.
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- LedChaser.
- use of soc.build_name in load/flash bitstream.
2020-05-21 09:14:33 +02:00
2eea786436
build/sim: rename dut to sim (for consistency with other builds).
2020-05-21 09:06:29 +02:00
a6cbbc9d69
integration/soc: set build_name to platform.name when not specified.
2020-05-21 09:05:45 +02:00
16417cb8f1
software/liblitespi: fix #endif location.
2020-05-20 23:20:45 +02:00
9bdb063b3e
Merge pull request #516 from antmicro/i2s_support_arty
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Add I2S support to Arty
2020-05-20 19:49:42 +02:00
c2e9a26ea8
Merge pull request #534 from fjullien/fix_litex_sim_warn
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litex/sim: fix compiler warnings
2020-05-20 19:49:04 +02:00
7c5f56c207
litex/sim: fix compiler warnings
2020-05-20 15:34:19 +02:00
ce49990084
Extend I2S capabilities
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This commit:
* adds the support for I2S standard mode,
* extends I2S left justified mode,
* allows to configure sample size for tx/rx in 1-32 bits range,
* implements I2S master mode,
* allows to concatenate channels or used the padded mode.
This required to rework the FSM.
2020-05-20 14:31:51 +02:00
2d6ee5aaf2
cores/cpu: add cv32e40p
2020-05-20 13:46:37 +02:00
ca8cb83424
software/bios/isr: add support for cv32e40p
2020-05-20 13:46:37 +02:00
2903b1bf80
litex_setup: add pythondata for cv32e40p
2020-05-20 13:46:37 +02:00
6fedaa704b
Merge pull request #533 from antmicro/fix-dummy-bits-function-name
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software/liblitespi/spiflash: fix dummy bits setup function name
2020-05-20 12:54:09 +02:00
ab41e27e4c
software/liblitespi/spiflash: fix dummy bits setup function name
2020-05-20 11:47:40 +02:00
d71152ef66
litex_setup: move requests import to avoid having to install it on travis.
2020-05-20 11:30:50 +02:00
9854fdd5f4
.travis: install requests package before running litex_setup.py.
2020-05-20 11:24:57 +02:00
bd0f21ba85
targets/netv2: remove LiteSPI integration (not mature enough to be directly integrated on targets).
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The LiteSPI integration can be prototype in the LiteSPI example designs. Once mature and
fully tested, we could integrate it to the targets.
2020-05-20 11:18:59 +02:00
80eca3000b
software/liblitespi/spiflash: review/simplify/update and test on arty.
2020-05-20 11:16:39 +02:00
4a1756208d
build/xilinx: simplify LITEX_ENV_ISE/VIVADO handling.
2020-05-20 10:00:39 +02:00
e91c317139
software/bios: cleanup includes and specify the lib in the include.
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This ease understanding from which lib the file is included and also allow
having simple filenames in the libs.
2020-05-20 09:55:19 +02:00
c3a03d0d99
software: create liblitespi and mode litespi code to it (with some parts commented out for now).
2020-05-20 09:32:45 +02:00
61238beeae
soc/software/bios: add autoconfiguration functionality for LiteSPI core
2020-05-20 09:16:07 +02:00
d389005550
litex_setup: add automatic update of litex_setup (because it also changes) and be sure we are on master branch before update.
2020-05-20 09:10:53 +02:00
939f546a05
Merge pull request #531 from gsomlo/gls-bios-linker
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software/bios: fix link order to avoid undefined symbol errors
2020-05-20 08:08:37 +02:00
c5524dbf20
software/bios: fix link order to avoid undefined symbol errors
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Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-05-19 16:20:58 -04:00
b4267a7901
build/xilinx: source settings64.sh automatically just before build if LITEX_ENV_ISE/LITEX_ENV_VIVADO environment variables are set.
2020-05-19 16:21:52 +02:00
de7e0ee9ff
integration/soc_core: avoid cpu_variant check if custom cpu_cls is passed.
2020-05-19 16:01:57 +02:00
6f8f0d2346
litex_setup: add litehyperbus and remove hyperbus core/test.
2020-05-19 15:49:25 +02:00
109fd2674a
integration/builder: simplify default output_dir to "build/platform".
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All SoC are now based on the same base class and naming was too complicated.
2020-05-19 13:59:56 +02:00
Florent Kermarrec
David Jablonski
Mateusz Hołenko
Jędrzej Boczar
Franck Jullien
Pawel Sagan
Piotr Binkowski
Jan Kowalewski
Gabriel Somlo