With nmigen/nmigen#a7b8ced, cli.py no longer defaults to generating
verilog code, so -t/--type has to be specified explicitly.
$ pytest test/test_targets.py -k test_variants_minerva
[...]
cli.py: error: specify file type explicitly with -t
DeprecationWarning: Using or importing the ABCs from 'collections' instead of from 'collections.abc' is deprecated since Python 3.3, and in 3.9 it will stop working
there is an async reset signal going to a FIFO
that can't be false_path'd because its timing is important
to making sure that the burst FIFO is reset to zero when
a miss happens in the burst cache. Unfortunately as designs
get full, the routability of this signal becomes difficult
and drives up the compile time and reduces quality of results.
There is enough time in the design to insert a single pipe stage
to alleviate the timing somewhat. This commit adds that register.
Instead of reading the 128 byte sdcard response after each operation,
read it only during debugging and/or when it's necessary (to retrieve
the relative card address, rca).
We no longer need a global sdcard_response array, and refactor the
various retrieval and reporting functions to contain a local buffer
for that purpose, only if/when necessary.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Factor out common portion of command functions. Also use appropriate
unsigned int width (e.g., uint16_t) for arguments.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Fix up earlier commit (#6c298cb7) and make the '-abc9' optional
argument to yosys' synth_ecp5 actually optional (and off by default)
in LiteX's trellis build infrastructure.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Make the DMA base address register 64-bit wide, to cover situations
in which the physical memory being accessed is above the 4GB limit
(e.g., on 64-bit systems with more than 4GB of provisioned physical
memory).
Also update DMA reader/writer setup call sites in the bios (currently
only used by litesdcard).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
LiteX is creating the SoC.dma_bus just after the CPU is declared, so declaring it in add_memory_buses was preventing it.
It's also more coherent to move it to __init__ since not related to the memory_buses.
The original CSR registers ordering (big: MSB on lower addresses) is not convenient
when the SoC is interfaced with a real OS (for example as a PCIe add-on board or
with a CPU running Linux).
With this, the original ordering is kept as default (big), but it can now be switched
to little to avoid software workarounds in drivers and should probably be in the future
the default for PCIe/Linux SoCs.
Florent Kermarrec
Xiretza
bunnie
Gabriel Somlo
Dolu1990
sadullah
Gwenhael Goavec-Merou
Pawel Sagan