5 commits

Author	SHA1	Message	Date
Florent Kermarrec	649cdeb265	liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen	2015-03-01 16:48:41 +01:00
Florent Kermarrec	b32a0e6f9e	liteeth: create example design derived from SoC that can be used on all targets with Ethernet pins	2015-02-28 23:33:00 +01:00
Florent Kermarrec	69e869893d	remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)	2015-02-28 11:36:15 +01:00
Florent Kermarrec	c4ebf244a1	litescope: move files and modify import to misoclib.tools.litescope	2015-02-28 10:33:46 +01:00
Florent Kermarrec	2c51adcd68	misoclib: better organization (create cores categories: cpu, mem, com, ...)	2015-02-28 09:40:44 +01:00

Renamed from misoclib/liteeth/example_designs/targets/base.py (Browse further)