The UART backend writes [read identifier, num_reads, addr] for
every read request.
Etherbone packets are able to include multiple read requests.
Therefore, it is beneficial to merge sequential read requests to reduce writes
(and possible latency overhead).
Benchmark:
A typical litescope fetch script with the following
signals [ddrphy.dfi,cpu.ibus.cyc,cpu.ibus.stb] results in 1 read for the
data_valid register and 24 sequential reads for the scope data per timestamp.
Fetching data for a capture length of 512 over a 921600 baud UART (arty board)
took:
205s (current master branch)
18s (with this merge function)
The proposed merger only merges read requests from one etherbone packet
at a time and doesn't change the read order.
This is the logical continuation of the recent change to avoid specific SoC classes.
A Zynq FPGA can be used with or without the PS7. When used without the PS7, a softcore CPU
can be used as with others FPGAs. When using the PS7, the softcore is replaced with the PS7
and connected to the SoC through one of the AXI GP interface.
An example is available on litex-boards.
When provided, the modules doing DMA shall connect the DMA to the dma_bus to allow the CPU(s) to manage cache coherency
and avoid the manual cache flushes.
This has been tested with VexRiscv SMP and LiteSDCard doing DMA while loading Linux binaries.
Fixes an issue with Vivado which crashes with SIGSEGV when building litex-buildenv at:
cc003bef3a
and litex bumped to 4a18b828bc,
with options:
CPU=mor1kx; CPU_VARIANT=linux; PLATFORM=arty; FIRMWARE=linux; TARGET=net
The only difference in Verilog is that we avoid creating new Interface and doing
`new_interface.connect(interface)`, so this shouldn't make any difference, but
this somehow generates the error in Vivado (tested on v2018.3 and v2019.2).
- Make sure MOSI is latched on start, MISO is stable during Xfer (last value).
- Allow clk_divider down to 2.
- improve test errors reporting with hex() on AssertEqual.
For example:
{
"Image": "0x40000000",
"bootargs": {
"r1": "0x12345678",
}
}
will copy Image to 0x40000000 and set r1 to 0x12345678.
By default, r1,r2,r3 are set to 0 and addr is the address if the last loaded image, so:
{
"Image": "0x40000000",
"rootfs.cpio": "0x40800000",
"rv32.dtb": "0x41000000",
"emulator.bin": "0x41100000",
}
is equivalent to:
{
"Image": "0x40000000",
"rootfs.cpio": "0x40800000",
"rv32.dtb": "0x41000000",
"emulator.bin": "0x41100000",
"bootargs": {
"r1": "0x00000000",
"r2": "0x00000000",
"r3": "0x00000000",
"addr": "0x00000000",
}
}
Florent Kermarrec
Christian Klarhorst
Jędrzej Boczar
Sean Cross
Piotr Binkowski
Ilia Sergachev
bunnie