aa57c7a25e
soc/cores/cpu/vexriscv_smp integration
2020-07-28 16:20:16 +02:00
f87513ab92
liblitesdcard/sdcard: increase SDCARD_CLK_FREQ to 50MHz.
2020-07-28 14:36:49 +02:00
9518ccf453
integration/soc/etherbone: expose ethcore (useful to combine udp/etherbone).
2020-07-27 19:57:29 +02:00
9e07623b61
integration/soc: fix dma_bus typo.
2020-07-27 11:06:09 +02:00
2034c563b0
Merge sequential reads for the UART litex_server backend
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The UART backend writes [read identifier, num_reads, addr] for
every read request.
Etherbone packets are able to include multiple read requests.
Therefore, it is beneficial to merge sequential read requests to reduce writes
(and possible latency overhead).
Benchmark:
A typical litescope fetch script with the following
signals [ddrphy.dfi,cpu.ibus.cyc,cpu.ibus.stb] results in 1 read for the
data_valid register and 24 sequential reads for the scope data per timestamp.
Fetching data for a capture length of 512 over a 921600 baud UART (arty board)
took:
205s (current master branch)
18s (with this merge function)
The proposed merger only merges read requests from one etherbone packet
at a time and doesn't change the read order.
2020-07-26 13:19:32 +02:00
1fdffdfd6b
targets: keep in sync with litex-boards.
2020-07-24 16:34:17 +02:00
8a0684b15e
Merge pull request #604 from antmicro/jboc/axi-lite
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Improve AXI Lite data width converters
2020-07-24 14:54:11 +02:00
879e6ffe73
soc/interconnect/axi: add basic AXI Lite up-converter
2020-07-24 13:47:18 +02:00
ed7211989f
Merge pull request #603 from enjoy-digital/socdoc-extensions
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Socdoc extensions
2020-07-24 16:42:23 +08:00
29b2baf927
doc: socdoc: document new `sphinx_extra_config` parameter
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This allows for appending additional configuration to `conf.py`.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-07-24 16:32:01 +08:00
3d16838d67
Merge pull request #602 from enjoy-digital/socdoc-extensions
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doc: socdoc: document `sphinx_extensions` parameter
2020-07-24 10:02:06 +02:00
dd366467ed
litex: add `sphinx_extra_config` to `generate_docs()`
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This allows us to append additional strings to the sphinx `conf.py`.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-07-24 16:01:54 +08:00
7fecfbf8e0
doc: socdoc: document `sphinx_extensions` parameter
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This adds documentation for `sphinx_extensions` which can be used to add
additional features to output.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-07-24 15:47:59 +08:00
32160e615f
soc/interconnect/axi: separate AXI Lite converter channels
2020-07-24 09:25:57 +02:00
8337039915
CHANGES: update.
2020-07-23 18:02:58 +02:00
041c7527ce
core/cpu: integrate Zynq as a classical CPU (Zynq7000), deprecate SoCZynq.
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This is the logical continuation of the recent change to avoid specific SoC classes.
A Zynq FPGA can be used with or without the PS7. When used without the PS7, a softcore CPU
can be used as with others FPGAs. When using the PS7, the softcore is replaced with the PS7
and connected to the SoC through one of the AXI GP interface.
An example is available on litex-boards.
2020-07-23 17:40:46 +02:00
8bdf6941a3
liblitesdcard/sdcard: use max divider of 256 (128 was not enough for the initial 400Khz clock frequency).
2020-07-22 23:15:36 +02:00
8f92034ddd
CHANGES: update.
2020-07-22 23:10:26 +02:00
99e88dfc0b
Merge pull request #600 from antmicro/jboc/axi-lite
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Implement AXI Lite interconnect
2020-07-22 23:03:07 +02:00
d38048baac
soc: add initial DMA bus support (optionally provided by CPU(s) for cache coherency).
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When provided, the modules doing DMA shall connect the DMA to the dma_bus to allow the CPU(s) to manage cache coherency
and avoid the manual cache flushes.
This has been tested with VexRiscv SMP and LiteSDCard doing DMA while loading Linux binaries.
2020-07-22 18:44:37 +02:00
a9d8b81385
test/axi: move all AXI Lite tests to separate file
2020-07-22 17:16:33 +02:00
367eb12240
soc/integration: use AXILiteSRAM when using bus_standard="axi-lite"
2020-07-22 17:16:33 +02:00
8ae501c391
test/axi: add crossbar stress tests
2020-07-22 17:16:33 +02:00
706bc25dc1
soc/integration: add bus standard parser arguments
2020-07-22 17:16:33 +02:00
32d9e212c5
soc/interconnect/axi: improve Timeout module and test it with shared interconnect
2020-07-22 17:16:33 +02:00
2cab7fbf0f
test/axi: add shared AXI Lite interconnect tests
2020-07-22 17:16:33 +02:00
3a08b21d44
soc/interconnect/axi: implement AXI Lite decoder
2020-07-22 17:16:33 +02:00
214cfdcaeb
soc/interconnect/axi: lock AXILiteArbiter until all requests have been responded to
2020-07-22 17:16:33 +02:00
baf23c9c9b
test/test_axi: add AXI Lite interconnect arbiter tests
2020-07-22 17:16:29 +02:00
a8a583d6b4
socinterconnect/axi: interconnect shared sketch
2020-07-22 17:16:26 +02:00
f47ccdae99
soc/interconnect/axi: point-to-point interconnect and timeout module with tests
2020-07-22 17:16:12 +02:00
b4c1120e3d
soc/integration: choose interconnect based on bus standard
2020-07-22 17:16:07 +02:00
69d8dd788d
soc/integration: add axi-lite standard to SoCBusHandler
2020-07-22 17:13:28 +02:00
2361abb12d
Merge pull request #599 from antmicro/gen-mmcm-pr
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litex-gen: add mmcm core
2020-07-22 14:52:26 +02:00
66c5f37133
litex-gen: add mmcm core
2020-07-22 12:34:32 +02:00
6b72f52c5d
boards: keep in sync with litex-boards.
2020-07-22 08:50:38 +02:00
1f27b7405e
soc/integration/add_sdcard: add direct connection to VexRiscv's dmabus for testing.
2020-07-21 19:54:42 +02:00
408d1a9f5d
cpu/vexriscv/system.h: update flush_cpu_dcache.
2020-07-21 19:43:00 +02:00
47ce15b431
interconnect/wishbone: add minimal UpConverter.
2020-07-21 19:35:14 +02:00
9fc488bdf6
Merge pull request #597 from antmicro/jboc/litex-buildenv-add-adapter-fix
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Fix Vivado crash when using 1:1 wishbone.Converter
2020-07-20 23:11:01 +02:00
b92519502a
Merge pull request #595 from betrusted-io/master
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wire up missing register bits.
2020-07-20 22:47:16 +02:00
87d7f6e72e
Merge pull request #598 from sergachev/master
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interconnect/csr_bus: fix paged access warning
2020-07-20 19:24:21 +02:00
8656ea9b67
interconnect/csr_bus: fix paged access warning
2020-07-20 18:23:09 +02:00
07bc589c41
fix/Vivado: don't instantiate wishbone.Converter in add_adapter when not needed
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Fixes an issue with Vivado which crashes with SIGSEGV when building litex-buildenv at:
cc003bef3a4a18b828bc
2020-07-20 15:26:21 +02:00
4a18b828bc
software/liblitesdcard/spisdcard: remove optimization on receive_block (not working on all configs) and increase max clk_freq to 20MHz.
2020-07-20 13:48:49 +02:00
100aa5a4ca
soc/cores/spi/SPIMaster: rewrite/simplify.
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- Make sure MOSI is latched on start, MISO is stable during Xfer (last value).
- Allow clk_divider down to 2.
- improve test errors reporting with hex() on AssertEqual.
2020-07-20 10:44:18 +02:00
53a567daef
wire up missing register bits.
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Not sure how they went missing...but just noticed them.
2020-07-19 03:00:25 +08:00
63c19ff45f
liblitesdcard/spisdcard: update comments.
2020-07-17 15:39:39 +02:00
1f34f6ef00
soc/cores/spi: make sure done and miso are synchronous.
2020-07-17 15:38:52 +02:00
754f140a9d
spisdcard: revert to 8-bit SPI, optimize spisdcardreceive_block and reduce clk to 12.5MHz for now.
2020-07-17 11:58:26 +02:00
Dolu1990
Florent Kermarrec
Christian Klarhorst
Jędrzej Boczar
Sean Cross
Piotr Binkowski
Ilia Sergachev
bunnie