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551 Commits 40 Branches 14 Tags 51 MiB
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551 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 546aa76aef software/dvimixer: support two channels 2013-05-09 13:41:21 +02:00
Sebastien Bourdeauducq 06064d33aa dvisampler/dma: better 8:8:8 -> 10:10:10 conversion 2013-05-09 11:27:24 +02:00
Sebastien Bourdeauducq c6d553e4e4 software/videomixer: interrupt-driven video passthrough 2013-05-09 10:52:43 +02:00
Sebastien Bourdeauducq fe87221d2b dvisampler/dma: reverse slot allocation order 2013-05-09 10:51:50 +02:00
Sebastien Bourdeauducq 2df4ff0ad9 dvisampler/dma: fix interrupt generation 2013-05-09 10:51:34 +02:00
Sebastien Bourdeauducq d685ed21fc dvisampler/dma: bugfixes 2013-05-08 22:50:40 +02:00
Sebastien Bourdeauducq 66b4bae7c8 top: connect dvisampler DMA IRQs 2013-05-08 22:31:42 +02:00
Sebastien Bourdeauducq b3d87e1c79 software/videomixer: use new DMA engine 2013-05-08 22:31:18 +02:00
Sebastien Bourdeauducq 29efa85dec dvisampler: new DMA engine (buggy) 2013-05-08 22:31:01 +02:00
Sebastien Bourdeauducq 89dbc37ece cif: do not generate write function for CSRStatus 2013-05-08 20:58:27 +02:00
Sebastien Bourdeauducq 8e76c960d9 timer, uart: EventSourceLevel -> EventSourceProcess 2013-05-08 18:11:42 +02:00
Sebastien Bourdeauducq e2d15b169a dvisampler: mostly working, very basic and slightly buggy DMA 2013-05-06 09:58:12 +02:00
Sebastien Bourdeauducq f82a16f3a3 software/videomixer: send to framebuffer 2013-05-06 09:56:49 +02:00
Sebastien Bourdeauducq 679d13c99c another attempt at fixing clock routing issues 2013-05-06 09:56:10 +02:00
Sebastien Bourdeauducq 784e96bb87 build.py: LOC clock generator components to limit breakage of the ISE shitware 2013-05-05 23:07:15 +02:00
Sebastien Bourdeauducq 11cbdf0d4f build.py: support single DVI sampler 2013-05-05 20:56:58 +02:00
Sebastien Bourdeauducq d05f3d22e0 chansync: bugfix 2013-05-05 15:07:57 +02:00
Sebastien Bourdeauducq 9c0d13b615 tb: add chansync 2013-05-05 15:07:36 +02:00
Sebastien Bourdeauducq d175e01876 dvisampler: connect sync polarity detection 2013-05-05 12:58:53 +02:00
Sebastien Bourdeauducq cb008a061c dvisampler/chansync: fix FIFO width 2013-05-05 12:58:24 +02:00
Sebastien Bourdeauducq ad01dc8a74 software/videomixer: use new resdetection regs 2013-05-05 11:58:43 +02:00
Sebastien Bourdeauducq ea20b74ed1 dvisampler/resdetection: use DE instead of hsync 2013-05-05 11:54:36 +02:00
Sebastien Bourdeauducq e3e1dcd547 dvisampler: add sync polarity detection module (thanks Lars for suggestions) 2013-05-05 11:53:38 +02:00
Sebastien Bourdeauducq 71e3bba228 dvisampler/decoding: hold C when DE=1 2013-05-05 11:51:48 +02:00
Sebastien Bourdeauducq 4259699d78 dvisampler: add RawDVISampler 2013-05-04 20:40:21 +02:00
Sebastien Bourdeauducq 63073319b0 dvisampler/datacapture: swap bit pairs 2013-05-04 20:38:50 +02:00
Sebastien Bourdeauducq 53e5c4f59c build: only add UCF constraints for the cores that are present 2013-05-02 23:56:09 +02:00
Sebastien Bourdeauducq 26c0261a4e Remove unneeded file 2013-05-01 17:13:40 +02:00
Sebastien Bourdeauducq 2e3c2611a6 software: put network code in a library 2013-05-01 00:12:13 +02:00
Sebastien Bourdeauducq 8222ee7f46 framebuffer: use DMA controller from Migen 2013-04-30 18:55:35 +02:00
Sebastien Bourdeauducq 43ac5c8471 Remove undriven reset signals 2013-04-25 20:19:49 +02:00
Sebastien Bourdeauducq de76faf757 Tell the Xilinx crapware that DCM_CLKGEN does not phase align, as some (but not all) of the ISE tools remark. 2013-04-25 20:18:45 +02:00
Sebastien Bourdeauducq 4ff1175dcf Use the Migen asynchronous FIFO 2013-04-25 19:43:26 +02:00
Sebastien Bourdeauducq d64b64501a minimac3: move psync 2013-04-25 18:36:45 +02:00
Sebastien Bourdeauducq 117b3b8ec7 adc: double-register asynchronous inputs 2013-04-19 12:32:12 +02:00
Werner Almesberger 0dca526a85 milkymist/adc/__init__.py: CounterADC - simple counter-based ADC 
This is a revised version of the counter-based ADC.
 2013-04-19 12:29:17 +02:00
Sebastien Bourdeauducq b018fcedc4 dvisampler/chansync: set synced to 0 when control tokens do not arrive at the same time 2013-04-16 22:21:03 +02:00
Werner Almesberger 1ab89d6a62 tftp.h, tftp.c: add tftp_put 2013-04-16 19:23:12 +02:00
Werner Almesberger 22f39b9d26 tftp.c: use symbolic constant for block size 2013-04-16 19:23:12 +02:00
Werner Almesberger 944dd5932d tftp.c (format_request): pass opcode as argument 2013-04-16 19:23:12 +02:00
Werner Almesberger aafb3ef8d7 tftp.c: use uintNN_t instead of "unsigned short", etc. 2013-04-16 19:23:12 +02:00
Werner Almesberger cdb5519272 tftp.h, tftp.c (tftp_get): make "buffer" void and use unsigned char internally 2013-04-16 19:23:12 +02:00
Werner Almesberger effa71a811 tftp.c: make "packet_data" unsigned and optimize strcpy+strlen 2013-04-16 19:23:12 +02:00
Werner Almesberger e0e447f0e0 tftp.c (rx_callback): simplify expressions containing unnecessary casts 2013-04-16 19:23:12 +02:00
Werner Almesberger 36613c7955 tftp.c: use symbolic constants for protocol opcodes 2013-04-16 19:23:12 +02:00
Werner Almesberger 65b807b63f microudp.c: avoid redundant accesses into multi-level structures 2013-04-16 19:23:11 +02:00
Sebastien Bourdeauducq 0d21711c1b dvisampler/chansync: use Record.raw_bits() 2013-04-14 17:06:29 +02:00
Sebastien Bourdeauducq 8914969760 dvisampler/clocking: insert DCM_CLKGEN before PLL 2013-04-14 16:53:19 +02:00
Sebastien Bourdeauducq f833bc9aa9 software/videomixer: use new csr.h 2013-04-14 16:33:00 +02:00
Werner Almesberger 7a6e56492c edid.py: sample SCL only every 64 clock cycles, to avoid bouncing 
Possibly due to SCL rising fairly slowly (in the 0.5-1 us range),
bouncing has been observed while crossing the "forbidden" region
between Vil(max) and Vih(min).

By lowering the sample rate from once per system clock to once
every 64 clock cycles, we make sure we sample at most once during
the bounce interval and thus never see a false edge. (Although we
may see a rising edge one sample time late, which is perfectly
harmless.)
 2013-04-12 22:48:46 +02:00