90f690ecce
README/BIOS: Bump year.
2023-02-16 09:10:01 +01:00
093c4fd166
tools/litex-term: completely eliminate multiprocessing
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Like commit 460fada3ac
2023-02-14 19:25:23 -06:00
106b2caaec
soc/cores/xadc: Fix refactoring issue (Zync -> Zynq :))
2023-02-13 15:43:43 +01:00
931b44ecd6
build/sim: Fix VIDEO flag generation.
2023-02-13 10:06:43 +01:00
44db314ddd
integration/soc/add_video_framebuffer: Add video_framebuffer region definition in linker.
2023-02-10 19:48:36 +01:00
3de5f20496
build/sim/litex_sim: Only compiles video module when used.
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Avoid additional SDL2 dependency for regular simulations.
2023-02-10 19:48:31 +01:00
1f08fe3286
build/sim/litex_sim: Add initial video module/support in simulation.
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Simulation with framebuffer:
litex_sim --with-sdram --with-video-framebuffer
Simulation with video terminal:
litex_sim --with-sdram --with-video-terminal
2023-02-10 19:48:24 +01:00
42f46c9c95
cpu/NaxRiscv fix nan-boxing on peripheral load
2023-02-10 17:21:53 +01:00
53e7492bd4
soc/cores/icap: Add clk_divider parameter and initial ICAPE3 support (Throught primitive parameters).
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Compiles on Ultrascale but still needs to be tested.
2023-02-10 16:19:42 +01:00
34422d2d91
cpu/NaxRiscv crt0.S now enable the FPU
2023-02-10 15:57:22 +01:00
ed48fb4d5d
tools/litex_client: Add --binary argument to display values in binary.
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Useful in some case to avoid decoding hexa manually.
2023-02-10 15:08:01 +01:00
5df1dacd18
cores/usb_ohci: Do minor review cleanups/changes.
2023-02-10 14:41:36 +01:00
d68bffb26e
Merge pull request #1597 from machdyne/master
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support multiple usb_ohci ports
2023-02-10 14:38:16 +01:00
211dfb2168
support multiple usb_ohci ports
2023-02-10 14:00:05 +01:00
2205a0c2c3
cores/xadc: Fix refactor issue.
2023-02-10 13:09:36 +01:00
408a68ba79
cores/dna: Add initial Ultrascale support.
2023-02-10 13:09:32 +01:00
b2053b7c52
cores/dna: Reduce default clk_divider to 2.
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To fix https://github.com/enjoy-digital/litex/issues/1516 .
2023-02-10 13:09:27 +01:00
838719c276
cores/xadc: Re-arrange and simplify code a bit.
2023-02-10 13:09:22 +01:00
8b36649c89
cores/xadc: Re-arrange and simplify code a bit.
2023-02-10 13:09:19 +01:00
92032b446c
cpu/NaxRiscv fix with_fpu typo
2023-02-10 10:07:50 +01:00
ac9bb70245
Merge pull request #1595 from suarezvictor/fpu
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add --with-fpu flag to Naxriscv CPU
2023-02-09 17:51:46 +01:00
2e5217352f
add --with-fpu flag to Naxriscv CPU
2023-02-09 13:26:45 -03:00
d256a5e3a8
Merge pull request #1594 from trabucayre/litex_setup_bashrc
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litex_setup: explain how to update permanently PATH env variable (#1589 )
2023-02-08 19:27:47 +01:00
64a1ecda6e
litex_setup: explain how to update permanently PATH env variable ( #1589 )
2023-02-08 18:59:46 +01:00
c054dc13d9
bios/cmds/cmd_litedram: Fix sdram_spd_handler compilation condition.
2023-02-08 10:05:55 +01:00
a56a178768
software/liblitesdcard: Add missing SPI_DONE mask on read status.
2023-02-06 13:09:45 +01:00
61bbfa3eaa
cores/spi/spi_master: Return raw/aligned mode on status register.
2023-02-06 13:08:53 +01:00
a6d9955c9d
software/liblitedram/accessors: Fix conditions for write_dq_bitslip functions compilations.
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Fixes #1583 .
2023-01-30 09:04:45 +01:00
8ad728cd22
software/liblitedram/accessors: Add seperators to improve readability.
2023-01-30 09:00:23 +01:00
647504d4c5
align fixup
2023-01-30 07:46:37 +01:00
fb94cb0551
Merge pull request #1512 from antmicro/liblitedram_cleanup
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Liblitedram cleanup
2023-01-26 18:50:51 +01:00
68877742b1
liblitedram: Add ability to access and adjust delays per DQ line
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Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
2023-01-26 13:12:37 +01:00
4c605020f0
liblitedram: Codebase cleanup
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Fix curly braces to be in the same line as the function header.
Fix function formating to be consistent in files.
Fix guards and add comments at the end of them.
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
2023-01-26 13:12:37 +01:00
58fda1a385
liblitedram: Move PHY accessors to a separate file
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They are independent from the training flow.
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
2023-01-26 13:12:37 +01:00
25b502dec8
liblitedram: define SDRAM_WLC_DEBUG
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SDRAM_WLC_DEBUG is 0 or 1 based on SDRAM_WRITE_LATENCY_CALIBRATION_DEBUG.
This reduces number of #ifdefs
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
2023-01-26 13:12:25 +01:00
8e848f6a13
liblitedram: #define MODULO
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It allows to replace repeating #ifdef SDRAM_PHY_DELAYS > 32
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
2023-01-26 13:12:25 +01:00
3c02323cfe
liblitedram: discard singular 1s that are surrounded by 0s
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They are most likely glitches and won't be stable.
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
2023-01-26 13:12:25 +01:00
cd89b62ff6
liblitedram: Fix LFSR
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LFSR only returns 1 random bit per lfsr() call,
so we should concatenate 8 consecutive calls to obtain 1 random byte
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
2023-01-26 13:12:25 +01:00
48f547885a
liblitedram: Correctly support single x4 IC
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Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
2023-01-26 13:12:25 +01:00
7b7fdadd26
liblitedram: Move pattern testing to its own function
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Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
2023-01-26 13:12:25 +01:00
155bf31e04
Merge pull request #1581 from trabucayre/gowinpll_fix_warnings
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soc/cores/clock/gowin_gw1n: fix size for ODSEL, FBDSEL, IDSEL, PSDA, DUTYDA, FDLY
2023-01-25 21:42:16 +01:00
975cc9ecdc
soc/cores/clock/gowin_gw1n: fix size for ODSEL, FBDSEL, IDSEL, PSDA, DUTYDA, FDLY
2023-01-25 20:47:30 +01:00
4b4fc7c6c0
cores/spi_flash: On Ultrascale: CS/DI/DO also need to be access through STARTUPE3, untested yet.
2023-01-25 12:19:10 +01:00
cc91f2ee3a
cores/spi_flash: Add USSPIFlash based on S7SPIFlash.
2023-01-25 10:31:40 +01:00
03342065c3
Merge pull request #1571 from enjoy-digital/naxriscv-merge
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cpu/Vexriscv-smp fix silent generation failure
2023-01-25 10:11:37 +01:00
04c240b847
Merge pull request #1579 from antmicro/msieron/fix-i2c
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I2C fixes
2023-01-24 10:11:06 +01:00
92977eb359
Merge pull request #1580 from trabucayre/libbase_fix_with_cpp
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soc/software/libXX/YY.h: adding extern C (required to link with cpp code)
2023-01-24 10:03:33 +01:00
1eabc36c84
soc/software/libXX/YY.h: adding extern C (required to link with cpp code)
2023-01-24 07:05:05 +01:00
7f829f9e44
libbase/i2c: use busy_wait_us instead of cdelay
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`cdelay` function is not a proper thing to count time.
It wouldn't count SoC clocks, but CPU clocks.
But even then, there are multiple instructions in `cdelay`:
- NOP
- decrement
- branch with compare
Assuming each instruction takes exactly 1 CPU cycle it is still wrong,
as we wait 3 time longer than requested.
But they don't take exactly 1 CPU cycle.
CPUs have caches, branch predictors, are out-of-order and so on.
So a much better way to count this time would be `busy_wait_us`.
I performed some test using vexriscv and Saleae Logic Analyzer:
vexriscv variant | requested I2C speed | actual (cdelay) | actual (busy_wait_us)
-----------------+---------------------+-----------------+----------------------
minimal | 50 kHz | 4 kHz | 38 kHz
minimal | 200 kHz | 15 kHz | 96 kHz
minimal | 400 kHz | 28 kHz | 137 kHz
-----------------+---------------------+-----------------+----------------------
lite | 50 kHz | 12 kHz | 40 kHz
lite | 200 kHz | 43 kHz | 115 kHz
lite | 400 kHz | 74 kHz | 180 kHz
-----------------+---------------------+-----------------+----------------------
standard | 50 kHz | 12 kHz | 45 kHz
standard | 200 kHz | 48 kHz | 159 kHz
standard | 400 kHz | 84 kHz | 311 kHz
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2023-01-23 18:34:37 +01:00
b122178876
libbase/i2c: don't enable pull-up after every bit
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Instead of enabling pull-up after every sent bit, enable it only after
sending all 8 bits.
This prevents some glitches from happening, where transition between
bits 0 to 0, produces a short spike.
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2023-01-23 18:34:37 +01:00
Florent Kermarrec
Thomas Watson
Victor Suarez Rovere
Dolu1990
inc
Gwenhael Goavec-Merou
Arne Jansen
Maciej Dudek
Michal Sieron