| .. |
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cpu
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cpu/vexriscv: update submodule
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2020-02-06 10:50:35 +01:00 |
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__init__.py
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litex: reorganize things, first work working version
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2015-11-07 17:48:55 +01:00 |
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bitbang.py
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soc/cores/bitbang: use new CSRField (no functional change)
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2019-09-16 16:56:00 +02:00 |
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clock.py
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cores/clock/create_clkout: rename clk_ce to ce, improve error reporting
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2020-01-24 09:10:31 +01:00 |
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code_8b10b.py
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cores/8b10b: use real Memory for 6b5b table (to improve timings on ECP5)
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2019-12-09 19:25:38 +01:00 |
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dna.py
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cores/dna: cleanup and add add_timing_constraints method
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2020-01-21 14:08:17 +01:00 |
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ecc.py
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soc/cores/ecc: improve readibility, uniformize with others cores
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2019-09-29 16:02:04 +02:00 |
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freqmeter.py
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soc/cores: rename frequency_meter to freqmeter and uniformize with others cores
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2019-09-29 16:08:39 +02:00 |
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gpio.py
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soc/cores/gpio: add GPIO Tristate
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2019-12-01 21:26:37 +01:00 |
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hyperbus.py
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soc/core: simplify/cleanup HyperRAM core
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2019-08-16 14:04:58 +02:00 |
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icap.py
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cores/icap: add add_timing_constraints method
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2020-01-21 14:08:36 +01:00 |
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identifier.py
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soc/cores: uniformize (continue)
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2019-09-29 17:04:21 +02:00 |
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jtag.py
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soc/cores/jtag: add Xilinx JTAG TAPs support and simple JTAG PHY (can be used for JTAG UART)
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2019-09-06 11:55:41 +02:00 |
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prbs.py
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soc/cores: uniformize (continue)
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2019-09-29 17:04:21 +02:00 |
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pwm.py
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soc/cores/pwm: remove debug print(n)
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2019-12-18 08:47:56 +01:00 |
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spi.py
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soc/cores/spi: use new CSRField (no functional change)
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2019-09-16 17:02:55 +02:00 |
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spi_flash.py
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Merge pull request #337 from gregdavill/spi-flash
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2020-01-09 13:24:17 +01:00 |
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timer.py
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cores: timer: clean up wording for timer documentation
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2020-01-02 16:24:12 +08:00 |
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uart.py
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soc/cores/uart: set rx_fifo_rx_we to True on UARTCrossover
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2020-01-17 06:32:00 +01:00 |
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up5kspram.py
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cores/up5ksram: optimize bus.adr decoding
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2019-07-22 07:55:47 +02:00 |
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usb_fifo.py
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soc/cores: uniformize (continue)
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2019-09-29 17:04:21 +02:00 |
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xadc.py
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cores/clock/xadc: ease DRP timings
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2020-01-19 20:57:14 +01:00 |
