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68 Commits

Author SHA1 Message Date
Clifford Wolf 3f55fb4ccb Improve testbench_verilator 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-25 13:04:49 +02:00
Clifford Wolf 247a19dd58 Add "make test_verilator" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-25 12:53:21 +02:00
Clifford Wolf f52f36762e Update riscv-gnu-toolchain to 1b80cbe 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-03 20:14:17 +02:00
Clifford Wolf df01132185 Update riscv-gnu-toolchain to bf5697a 2017-11-19 01:54:56 +00:00
Clifford Wolf d9d5220071 Update riscv-gnu-toolchain to git rev e9f5458 2017-10-19 17:18:47 +02:00
Clifford Wolf a412d3ea69 Add "make test_rvf" 2017-09-13 18:45:57 +02:00
Clifford Wolf 98ee8098b9 Add testbench_ez 2017-07-27 21:36:38 +02:00
Clifford Wolf f295b900bc Add RVFI to AXI and WB wrappers modules, Add RVFI monitor support to test bench 2017-05-27 19:58:44 +02:00
Clifford Wolf a13512c86a Update riscv-gnu-toolchain to git rev 4e51f26 2017-05-05 11:32:22 +02:00
Clifford Wolf 3675375072 Update riscv-gnu-toolchain to git rev 0c8f87d 2017-04-07 11:43:05 +02:00
Clifford Wolf 5d2ff0129a Add GIT_ENV Makefile variable (for things like http proxy settings) 2017-03-15 16:35:02 +01:00
Antony Pavlov 8e55b93541 Makefile: use automatic variables in testbench rules 
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
 2017-03-15 07:15:31 +03:00
Antony Pavlov a25597532d WIP: add WISHBONE testbench 
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
 2017-03-14 09:37:05 +03:00
Clifford Wolf ce862f09f5 Rename "testbench_vcd" make target to "test_vcd", remove "view" 2017-03-12 10:59:22 +01:00
Clifford Wolf 75830805b8 Rename "make testbench.vcd" to "make testbench_vcd" so VCD file is not removed on Ctrl-C 2017-02-21 11:17:43 +01:00
Clifford Wolf 8e5deeb0cb Update riscv-gnu-toolchain to git rev 914224e 2017-01-13 17:02:56 +01:00
Clifford Wolf 55da6c7cd1 Some build fixes for new riscv-gnu-toolchain 2016-12-17 13:00:30 +01:00
Clifford Wolf 56dc5b3549 Improved "git cherry-pick" for riscv-binutils-gdb a5971eca338 2016-12-17 10:06:03 +01:00
Clifford Wolf 62c7b96b1c Updated riscv-gnu-toolchain to git rev 34e199d + riscv-binutils-gdb commit a5971eca338 2016-12-17 09:51:10 +01:00
Clifford Wolf b8cecc9148 Updated riscv-gnu-toolchain to git rev e3e50c5 2016-12-15 14:43:21 +01:00
Clifford Wolf 92df4b35ee Merge branch 'master' into riscv-gnu-toolchain-update 2016-12-15 14:23:20 +01:00
Clifford Wolf 0bea8428f3 Suppress iverilog warnings re parameters in "make test_synth" 2016-12-15 13:11:26 +01:00
Clifford Wolf 9d873cac92 Minor changes and build fixes for new riscv-gnu-toolchain 2016-12-10 12:09:15 +01:00
Clifford Wolf b8af714546 Added RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX Makefile variable 2016-12-09 11:47:05 +01:00
Clifford Wolf f6b009c4c9 Updated riscv-gnu-toolchain 2016-12-08 14:09:09 +01:00
Clifford Wolf 117586ff19 Added RISC-V Formal Interfcae (RVFI) 2016-11-23 03:02:02 +01:00
Clifford Wolf 5bea3f9917 Added more asserts for the memory interface 2016-09-13 19:34:14 +02:00
Clifford Wolf 44d6feba2a Using assertpmux in "make check" 2016-09-07 12:40:19 +02:00
Clifford Wolf 8bfd7c166b Added generic "make check-<solver>" rule 2016-09-03 15:16:24 +02:00
Clifford Wolf 12c218c1b3 Using new yosys write_smt2 cmdline 2016-08-30 14:37:21 +02:00
Clifford Wolf 28fe45ffe9 Added more asserts to picorv32, more smtbmc examples 2016-08-29 17:23:00 +02:00
Clifford Wolf 98d248d2c2 Finalized tracer support 2016-08-26 14:54:27 +02:00
Clifford Wolf 7094e61af7 Added tracer support (under construction) 2016-08-25 14:15:42 +02:00
Clifford Wolf bec8d6a6b9 Fixed "make check" for new yosys-smtbmc cmdline 2016-08-20 19:18:49 +02:00
Clifford Wolf 22d73aafed Updated riscv-gnu-toolchain to git rev 7e48594 2016-08-17 01:06:10 +02:00
Clifford Wolf 30e815d104 Updated riscv-gnu-toolchain version to git rev 13f52d2 (2016-05-31) 2016-05-31 16:21:24 +02:00
Clifford Wolf 88299374cf Updated riscv-gnu-toolchain to 34db4e0 (now using gcc 6.1.0) 2016-05-05 12:06:29 +02:00
Clifford Wolf 6c69b3812e Using .vvp instead of .exe for iverilog executables 2016-05-04 08:57:16 +02:00
Clifford Wolf 8d453a1dd4 Building the tools in sequence is much faster 2016-04-11 22:54:15 +02:00
Clifford Wolf 5d422d7637 Added "make build-tools" 2016-04-11 12:46:29 +02:00
Clifford Wolf bc85a4c110 Updated riscv-gnu-toolchain (c.addi16sp bugfix) 2016-04-10 12:03:09 +02:00
Clifford Wolf df7f5915d7 Added documentation for COMPRESSED_ISA parameter 2016-04-09 14:35:17 +02:00
Clifford Wolf 36cdf83b3f Added "make clean" handling of riscv-gnu-toolchain-riscv32* directories 2016-04-09 12:51:50 +02:00
Clifford Wolf 579b60aef9 Added "make build-riscv32i-tools" and friends 2016-04-09 12:29:19 +02:00
Clifford Wolf 714f7d9cfa Merged axi4_memory.v and picorv32_wrapper.v back into testbench.v 2016-03-02 12:50:52 +01:00
Olof Kindgren 9591ae9f7d Split out verilator-incompatible code to top-level testbench 
Verilator doesn't handle verilog code that deals with time, such
as delayed signals or the repeat task. Clock and reset generation
are therefore moved to a separate file that can be replaced by
a verilator module. VCD generation is also affected by this.
 2016-02-18 22:47:15 +01:00
Olof Kindgren 8343315aa7 Break out AXI4 memory to a separate module 
This commit also adds support for setting the AXI_TEST and VERBOSE
defines as plusargs or parameters
 2016-02-18 21:26:18 +01:00
Clifford Wolf c4c477180e Merged various testbench changes from compressed ISA branch 2016-02-03 16:33:01 +01:00
Clifford Wolf 8d9f048785 Using riscv32-unknown-elf- toolchain 2015-11-03 18:59:12 +01:00
Clifford Wolf 8eaeebf486 Progress in "make check" 2015-10-15 15:45:19 +02:00