Commit Graph

313 Commits

Author SHA1 Message Date
Peter McGoron 26fcd0af59 waveform sucessfully runs 2024-03-14 10:02:47 +00:00
Peter McGoron 3fac5747cc micropython control of SPI works (as far as I can tell) 2024-03-12 10:01:46 +00:00
Peter McGoron df9a7dcd8d Precompile Micropython to bytecode: Document
This reduces load times a little bit, and also allows for documentation
inside the modules without bloating up memory.
2024-03-12 01:13:23 +00:00
Peter McGoron 2e98c0229d Upsilon standard library; integrate waveform; overhaul code generation
1. Add a new Upsilon MicroPython standard library in the linux/
   subdirectory. This puts all the submodules into classes with methods
   for ease of access.
2. Totally rewrite mmio.py code generation. Instead of just dumping
   registers, the build system now instantiates classes which
   encapsulate the module in question.
3. Split the PicoRV32 special register interface away from the PicoRV32.
   It is now the PeekPokeInterface, which will be used in the future to
   implement register control for Waveform and SPI.
4. Integrate Waveform into the design. Has not been tested yet.
2024-03-11 04:31:30 +00:00
Peter McGoron 223d2f98c6 add pre_finalize() to PreemptiveInterface
CSR scans run *before* do_finalize() is called. This is a silent
failure: The signals get generated but the CSR is not in the csr.json
file or the generated verilog.

pre_finalize() is a function that must be called when all masters are
added to the module. This will generate the CSR before finalization,
(hopefully) ensuring that the CSR is added to the CSR bus.

I need to figure out a way to excise manual use of the CSR bus from the
design. Future options may include having a PreemptiveInterface
control module sitting in front of the PreemptiveInterfaces that exposes
the control lines as a Wishbone register.
2024-03-07 15:59:08 +00:00
Peter McGoron 487d638aa5 Integrate Waveform into SoC; Rework PreemptiveInterface
New master buses can be added to PreemptiveInterface throughout the
code, simplifying the main SoC code. This removes the requirement that
the amount of masters to the interface needs to be known at
instantiation time.
2024-03-06 21:17:51 +00:00
Peter McGoron baaea5a2cc waveform: finish basic tests 2024-03-03 23:05:29 +00:00
Peter McGoron 525e2a1615 waveform: simulation checks that loop runs multiple times 2024-03-03 22:48:58 +00:00
Peter McGoron 1d85e2307d waveform: write and start simulation 2024-03-03 22:35:19 +00:00
Peter McGoron 35f55c8e1d swic.py: Fix generation of constants for control loop parameters 2024-02-28 13:37:50 +00:00
Peter McGoron 75d7f298e2 Documentation and register location generation 2024-02-28 13:28:06 +00:00
Peter McGoron da1e9238ab unify region generation and added SPI to PicoRV32 2024-02-27 03:48:22 +00:00
Peter McGoron 6f61d7db7a Documentation, fix parameter passing
1. Started writing a lot of documentation on how Upsilon is
   structured. This will replace the very outdated documentation.
2. Fixed parameter access and writing. This is also a more generic
   interface that can be used for Pico CPUs that implement different
   routines.
2024-02-26 06:02:48 +00:00
Peter McGoron 3dd64034d2 fix compile by adding SPI makefile 2024-02-26 04:11:09 +00:00
Peter McGoron 6b9e594b50 Successfully read PicoRV32 registers 2024-02-26 00:47:43 +00:00
Peter McGoron 88e3d15dd8 Get PicoRV32 to execute code
1. Update LiteX to 2023.12. This update adds wishbone bus addressing
   modes. Before this update, all wishbone buses used word addressing.
   For example, 0x0 mapped to word 0, 0x0 mapped to word 1, etc. This
   caused problems with the PicoRV32 and other modules, which are byte
   addressed.
2. Use adapter to convert between byte and word addressing. The SRAM is
   word addressed. The PicoRV32 shifts the address down by two bits to
   address the correct word. The PicoRV32 core seems to expect this.
3. Add debug register output. This is not working yet.
4. Use LiteX PicoRV32 wishbone adapter instead of PicoRV32 default. This
   seems to be simpler (combinatorial not synchronous).
5. Add some documentation.
6. Seperate config to new config file.
2024-02-25 18:58:34 +00:00
Peter McGoron 3785e3498d reorganize litex code 2024-02-22 15:35:31 +00:00
Peter McGoron f5b14d51ab picorv32 now runs: debugging outputs 2024-02-22 04:58:59 +00:00
Peter McGoron 67c670cb5c Use Decoder and custom region code for PicoRV32
The PicoRV32 SoC bus generator conflicts with the main SoC bus
generator, which causes the address locations in the generated verilog file
to be different from the set locations. This code uses custom region
classes in soc.py and the Decoder class directly, which is similar to
what the finalization of the SoC class uses, and is based on the LiteEth
code does.
2024-02-21 23:39:21 +00:00
Peter McGoron 06cf8807c3 Progress on PicoRV32
1) The PicoRV32 bus was not generated correctly. Running "finalize" on
   the bus, which is what the SoC does, does not generate the bus logic
   correctly. I don't know if  this is a bug or if the SoC bus generator is
   only meant to be used in the main SoC.

   Currently the bus logic is copied from the LiteX finalize code.

2) Add test micropython code to load code.

3) Removed BRAM. The Wishbone cache was messing with the direct
   implementation of the BRAM because the BRAM did not implement all the
   bus features correctly. LiteX has a Wishbone "SRAM" module, and despite
   it's name it can also generate BRAM if there are available BRAM. This is
   how the ROM and the startup RAM are implemented. The PicoRV32 ram
   is now using this SRAM.
2024-02-20 15:36:53 +00:00
Peter McGoron 0cfa172a89 This compiles and runson the Arty A7-100 2024-02-18 02:34:37 +00:00
Peter McGoron 4e3df09bb8 more cleanup and bug finding 2024-02-08 12:57:22 +00:00
Peter McGoron a10ad772bc boot currently loops at LiteX logo: this fixes it 2024-02-04 18:59:35 +00:00
Peter McGoron 7af775e46d update.gitignore 2024-02-04 17:10:08 +00:00
Peter McGoron d06e0a8589 update README.md 2024-02-04 17:00:35 +00:00
Peter McGoron 2f92199c37 write picorv32 test code 2024-02-04 16:54:10 +00:00
Peter McGoron f7d6fbee2f remove explicit finalize, is not needed and probably out of order 2024-02-04 14:50:19 +00:00
Peter McGoron c3980f64da Correctly finalize picorv32 module
I think LiteX's SoCIORegions are reserved regions. Non-cached regions
are then placed inside these reserved regions. Each module also has
a "do_finalize" method that runs at code generation.
2024-02-04 14:47:39 +00:00
Peter McGoron 9f76e03028 Minor SPI fixes and Interconnect fix
The previous code did not properly assign all values on all cases,
and did not properly assign values (master interfaces, which are
poorly named because they are the interfaces to the master, connect
to the slave lines directly in the interconnect)
2024-02-03 00:33:52 +00:00
Peter McGoron 68ce1f4f64 Change SoC IO Region declarations
LiteX has some distinction between SoCIORegions and SoCRegions that
I don't quite get. SoCRegion has to be cached, SoCIORegion is not
cached. LiteX (Migen?) also does not allow you to reach into
submodules to read values.
2024-02-02 23:38:42 +00:00
Peter McGoron b4a8fdab56 fix misc build errors 2024-02-02 22:46:58 +00:00
Peter McGoron fbd3dcef2e picorv32 integration, take 1 2024-02-02 15:24:18 -05:00
Peter McGoron 9db87cb8ee bram: integrate into SoC using Wishbone bus, and note alignment 2024-01-21 04:38:34 +00:00
Peter McGoron 63a347a18f fix Makefile bram codegen 2024-01-20 20:43:12 +00:00
Peter McGoron 8c7f57c8e9 fix compile errors for soc.py 2024-01-20 20:35:16 +00:00
Peter McGoron 565847f7c5 merge ip changes 2024-01-20 20:28:43 +00:00
Peter McGoron 03d9d7ea8f add bram 2024-01-20 15:23:40 -05:00
Peter McGoron cd2be977bc fix SoC compile 2024-01-18 19:48:34 +00:00
Peter McGoron 0bb27e9b03 use add_constant() to modify network settings in SoC 2024-01-18 10:41:51 -05:00
Adam Mooers 8b5204978b
Merge pull request #2 from AdamMooers/initial_functionality
Initial functionality
2023-08-23 22:11:44 -04:00
Adam Mooers a9c6c1080c Added makefile formatting 2023-08-23 22:09:34 -04:00
Adam Mooers 2863c9a2d2 Fixed bug where scp silently switches to sftp on new version of openssh 2023-08-20 00:47:04 -04:00
Adam Mooers b1fb245908 Cleaned up Makefile formatting and clarified tar comment 2023-08-17 11:53:18 -04:00
Adam Mooers e4a92f5e16 Fixed ip address in host config 2023-08-16 16:27:05 -04:00
Adam Mooers e0c3bedcee Updated makefile to automatically select the right openFPGALoader 2023-08-16 15:49:44 -04:00
Adam Mooers 2a97f0a197 Fixed line which combined two git commands 2023-08-15 21:11:20 -04:00
Adam Mooers 37c734f7be Fixed a typo in the top-level README 2023-08-15 17:59:14 -04:00
Adam Mooers f41ab72483 Added relative links to documentation 2023-08-15 17:58:03 -04:00
Adam Mooers 7ef5803cd3 Migrated changes from the upsilon-docker repo to this repo 2023-08-15 17:32:25 -04:00
Adam Mooers 5be3459332 Moved network from to 192.168.2 because 192.168.1 is very common 2023-08-08 23:59:34 -04:00