Commit Graph

313 Commits

Author SHA1 Message Date
Peter McGoron 888ce66f52 add to programmers manual 2023-04-03 04:39:16 +00:00
Peter McGoron 6e9d234dc0 logging and error handling 2023-04-03 03:29:56 +00:00
Peter McGoron 6b27356820 remove outdated creole stub 2023-04-03 03:14:28 +00:00
Peter McGoron 1911d58725 creole interface 2023-04-03 03:14:19 +00:00
Peter McGoron 5b390929f5 update programmers manual 2023-04-03 03:14:05 +00:00
Peter McGoron a26df53af5 add wf_running to generate_csr_locations.py 2023-04-03 03:13:54 +00:00
Peter McGoron c5019de982 make read_buf read until it fills up all of bufptr 2023-04-02 21:46:10 +00:00
Peter McGoron e5e8b28676 update creole 2023-04-02 21:37:37 +00:00
Peter McGoron 11f7cfd388 refactor soc.py base.v interface 2023-04-02 21:35:51 +00:00
Peter McGoron 69f16264dd add assertions 2023-04-02 21:25:19 +00:00
Peter McGoron 66ea3ca0ea waveform.v
fix potential hang in waveform.v
2023-04-02 21:20:26 +00:00
Peter McGoron 657b400666 Revert "roll back to creole master"
This reverts commit aa77f0f494.
2023-04-02 01:56:30 +00:00
Peter McGoron aa77f0f494 roll back to creole master 2023-04-02 01:46:30 +00:00
Peter McGoron cbdd0daaa6 creole interface 2023-03-23 22:25:29 +00:00
Peter McGoron 8006853e6c creole_interface.c 2023-03-20 19:06:22 +00:00
Peter McGoron a7da03f4b9 fix generate_csr_locations.py 2023-03-20 15:07:52 -04:00
Peter McGoron 908be977f5 merge 2023-03-20 17:59:37 +00:00
Peter McGoron a55c791add .gitignore 2023-03-20 13:59:01 -04:00
Peter McGoron f90348aff9 arty.xdc for synth test 2023-03-20 13:58:35 -04:00
Peter McGoron 0259523d20 add yosys synth test for control loop 2023-03-20 13:57:42 -04:00
Peter McGoron 93c92b9f55 add test scripts for synthesizing ram fifo 2023-03-20 13:57:15 -04:00
Peter McGoron 368bbb6e2b update generate_csr_locations 2023-03-16 18:53:37 +00:00
Peter McGoron 50ef091578 move preprocessed generation to common makefile 2023-03-16 16:32:03 +00:00
Peter McGoron 23d29abdd7 programmers manual 2023-03-16 16:31:53 +00:00
Peter McGoron 55fc252382 pass yosys 2023-03-15 17:08:55 -04:00
Peter McGoron fbbd41c95e codegen 2023-03-15 14:57:22 -04:00
Peter McGoron ca8078f9d6 quick hack: pre-prepreprocess verilog files 2023-03-15 18:47:20 +00:00
Peter McGoron ef8ce874ba .gitignore 2023-03-15 18:31:32 +00:00
Peter McGoron 411c0c52c1 add control_loop_cmds header generators 2023-03-15 18:30:30 +00:00
Peter McGoron 953e42b80c change control_loop to m4 scripts, add common makefile 2023-03-15 18:30:08 +00:00
Peter McGoron 7af907ffb4 soc.py: fix syntax errors 2023-03-15 03:04:27 -04:00
Peter McGoron fefa6409cf soc.py: add missing waveform pins 2023-03-15 06:30:59 +00:00
Peter McGoron 0f40b2cd95 base: add new waveform pins 2023-03-15 06:29:19 +00:00
Peter McGoron 9c89453c77 .gitignore 2023-03-15 06:25:32 +00:00
Peter McGoron 4142a0a1b4 simulate waveform.v 2023-03-15 06:24:28 +00:00
Peter McGoron 0b6e740af4 GUIDELINES: update 2023-03-14 15:59:17 +00:00
Peter McGoron c8f2cf1f7a spi_switch: fix dangling else 2023-03-14 15:43:34 +00:00
Peter McGoron 90a49b6091 test and simulate spi_switch 2023-03-14 15:42:41 +00:00
Peter McGoron 36e5b964d5 lint base.v 2023-03-14 04:06:42 +00:00
Peter McGoron d198273155 add base.m4 2023-03-14 01:40:17 +00:00
Peter McGoron eadf374cd0 lint waveform.v 2023-03-10 22:59:26 +00:00
Peter McGoron 295eb8fad8 add base.v 2023-03-09 04:17:41 +00:00
Peter McGoron 89938a2ff6 move autoapproach to possibly useful waveform module: not yet tested 2023-03-03 18:30:00 +00:00
Peter McGoron 05f8878751 add submodules and switch 2023-03-03 08:06:50 +00:00
Peter McGoron 3a4224ff5b merge 2023-02-25 21:17:18 +00:00
Peter McGoron 92091d0982 stuff 2023-02-25 21:17:04 +00:00
Shell-ac 556db1f361
Add files via upload
Verilog signal propagation testbench for the intsat module
2023-01-30 14:09:49 -05:00
Peter McGoron f88e0ef15c Merge branch 'master' of ssh://github.com/phm19a/upsilon 2023-01-30 13:54:58 +00:00
Peter McGoron b3a79f41ec refactoring: move dma simulation to verilog 2023-01-30 13:54:17 +00:00
Peter McGoron 4afc655104 more refactoring 2023-01-30 13:07:34 +00:00