Peter McGoron
|
d9f4a40c6d
|
update GUIDELINES.md
|
2022-11-17 18:39:48 -05:00 |
Peter McGoron
|
82ff659a44
|
add DAC ramp
|
2022-11-17 17:32:32 -05:00 |
Peter McGoron
|
0907a76c22
|
import spi v0.2
|
2022-11-14 08:43:16 -05:00 |
Peter McGoron
|
50ea679e02
|
Rewrite control_loop_math and simulate
Replace specialized math nodes with single multiplier: each constant
must be resized to fit in the multiplier. Simplifies design at the
cost of speed.
|
2022-11-13 18:03:55 -05:00 |
Peter McGoron
|
88c42a9f4a
|
add printing of fixed point values in C++
|
2022-11-12 01:44:30 -05:00 |
Peter McGoron
|
c21e2bbb63
|
add calculate dt module with simulation
|
2022-11-11 22:42:06 -05:00 |
Peter McGoron
|
7637a1db9a
|
import updated boothmul
|
2022-11-11 22:14:50 -05:00 |
Peter McGoron
|
45f815c5d3
|
changes
|
2022-11-11 21:57:58 -05:00 |
Peter McGoron
|
7a341a9632
|
yosys does not like calculated parameters
|
2022-10-30 15:37:45 -04:00 |
Peter McGoron
|
732be44a8d
|
add guidelines
|
2022-10-30 15:37:08 -04:00 |
Peter McGoron
|
ba901a80d7
|
separate math into other file
|
2022-10-28 17:31:23 -04:00 |
Peter McGoron
|
653040fb67
|
clarify licenses
|
2022-10-27 17:55:57 -04:00 |
Peter McGoron
|
440f144180
|
fixed fixed point algorithms in python
|
2022-10-27 17:55:12 -04:00 |
Peter McGoron
|
4f85146d61
|
add cycle count for each iteration
|
2022-10-23 14:21:31 -04:00 |
Peter McGoron
|
0a435f6dc8
|
rename control loop verilog simulation top level module to more descriptive name
|
2022-10-22 01:58:37 -04:00 |
Peter McGoron
|
7971f8ea98
|
change heading
|
2022-10-22 01:55:56 -04:00 |
Peter McGoron
|
644929ef8a
|
move documentation to other file
|
2022-10-22 01:55:15 -04:00 |
Peter McGoron
|
91cbf56b02
|
integrate adding stored dac value into rtrunc
|
2022-10-22 01:52:58 -04:00 |
Peter McGoron
|
f361cac01b
|
make values update on the start of the control loop, and make resets only take effect after the control loop has completed an iteration
|
2022-10-21 17:38:07 -04:00 |
Peter McGoron
|
12686391ee
|
use integer saturation for dac value adjustment
|
2022-10-20 19:43:13 -04:00 |
Peter McGoron
|
2a300b9438
|
write total value to dac, not adjustment vlaue
|
2022-10-20 15:42:24 -04:00 |
Peter McGoron
|
c42e2fe419
|
add write-read interface to control loop
|
2022-10-18 07:10:06 -04:00 |
Peter McGoron
|
dc2b1fe339
|
move SPI master out of control loop design
|
2022-10-17 14:37:37 -04:00 |
Peter McGoron
|
0ef00c15d7
|
move simulators to the same directory of the simulated core
|
2022-10-17 00:45:19 -04:00 |
Peter McGoron
|
029cc53c5f
|
some more changes
|
2022-10-17 00:44:30 -04:00 |
Peter McGoron
|
5125719a1f
|
move control loop stub code to control loop rtl
|
2022-10-12 08:48:34 -04:00 |
Peter McGoron
|
7ca119d45f
|
soc.py legal
|
2022-09-17 00:58:15 -04:00 |
Peter McGoron
|
22ced7dcc8
|
add SPI link
|
2022-09-17 00:37:42 -04:00 |
Peter McGoron
|
e8bbc1303e
|
add readme and COPYING
|
2022-09-17 00:35:47 -04:00 |
Peter McGoron
|
0298299402
|
add everything im working on
|
2022-09-16 18:01:34 -04:00 |
Peter McGoron
|
7bf784e6bc
|
add jsmn.h
|
2022-08-02 19:44:09 -04:00 |
Peter McGoron
|
2c7ef45254
|
move tests to remove clutter
|
2022-08-02 19:44:04 -04:00 |
Peter McGoron
|
898b2e8cba
|
ethernet communication
|
2022-08-01 14:44:09 -04:00 |
Peter McGoron
|
7de27a2408
|
change converter code to drive new verilog
|
2022-07-27 09:33:11 -04:00 |
Peter McGoron
|
1add778b51
|
change CSR types
|
2022-07-27 09:32:49 -04:00 |
Peter McGoron
|
01cbcb5fae
|
add verilog SPI
|
2022-07-21 17:07:52 -04:00 |
Peter McGoron
|
38c15cec45
|
add floating point flag to threads
|
2022-07-18 12:46:39 -04:00 |
Peter McGoron
|
52e2dada98
|
rename dac_adc_test_main.c to test_dac_adc_main.c
|
2022-07-15 13:56:58 -04:00 |
Peter McGoron
|
52ecbd1901
|
io.c: document ADC code
|
2022-07-15 11:01:03 -04:00 |
Peter McGoron
|
683f85df00
|
add .gitignore
|
2022-07-14 15:48:07 -04:00 |
Peter McGoron
|
4370ee3d69
|
add dac_adc test
|
2022-07-14 15:47:31 -04:00 |
Peter McGoron
|
618bf3266a
|
fix io.c includes and logging
|
2022-07-14 15:46:59 -04:00 |
Peter McGoron
|
9a0d590cf1
|
dont bring in csr locations when not necessary
|
2022-07-14 15:46:38 -04:00 |
Peter McGoron
|
ffae5ecdf9
|
add sign extension, header
|
2022-07-14 15:11:22 -04:00 |
Peter McGoron
|
592939f5bd
|
change pinout
|
2022-07-14 15:10:58 -04:00 |
Peter McGoron
|
f6c90ff3d1
|
ADC code simplification; use lowest common denominator instead
|
2022-07-14 10:14:09 -04:00 |
Peter McGoron
|
75e1001452
|
checks and misc fix
|
2022-07-14 09:27:18 -04:00 |
Peter McGoron
|
5287366140
|
start DAC and ADC io
|
2022-07-13 15:36:36 -04:00 |
Peter McGoron
|
32b96eaf9a
|
add macros for number of adcs and dacs
|
2022-07-13 15:35:42 -04:00 |
Peter McGoron
|
60d9b63163
|
testing PMOD DAC output successful
|
2022-07-13 14:12:06 -04:00 |