Commit Graph

84 Commits

Author SHA1 Message Date
Peter McGoron adb81e201e fix dac simulation 2022-11-21 22:56:40 -05:00
Peter McGoron 5ff6b279b0 reverify math 2022-11-21 22:24:37 -05:00
Peter McGoron 79cae3dd66 (somewhat) fix counter 2022-11-21 22:08:25 -05:00
Peter McGoron cfb0f92528 fix adc_sim 2022-11-21 22:04:46 -05:00
Peter McGoron 5909f548d5 control loop simulator passes lint 2022-11-21 21:41:50 -05:00
Peter McGoron 0114c449c3 correct simulation of control loop 2022-11-19 12:55:55 -05:00
Peter McGoron a0450fb0ff control_loop_math: fix compile errors and verify simulation 2022-11-18 19:27:29 -05:00
Peter McGoron 0c10dc921c more work on control_loop
* Make SPI masters internal to control loop module
* Rename commands to use I isntead of alpha
* add ADC value -> DAC value conversion to control loop math
2022-11-18 19:11:56 -05:00
Peter McGoron 3a23ac6e92 control_loop; add dirty bit to decrease the amount of comparisons 2022-11-17 19:14:24 -05:00
Peter McGoron 29e0e8dfb3 integrate control_loop_math into control_loop 2022-11-17 19:07:21 -05:00
Peter McGoron 82ff659a44 add DAC ramp 2022-11-17 17:32:32 -05:00
Peter McGoron 0907a76c22 import spi v0.2 2022-11-14 08:43:16 -05:00
Peter McGoron 50ea679e02 Rewrite control_loop_math and simulate
Replace specialized math nodes with single multiplier: each constant
must be resized to fit in the multiplier. Simplifies design at the
cost of speed.
2022-11-13 18:03:55 -05:00
Peter McGoron 88c42a9f4a add printing of fixed point values in C++ 2022-11-12 01:44:30 -05:00
Peter McGoron c21e2bbb63 add calculate dt module with simulation 2022-11-11 22:42:06 -05:00
Peter McGoron 7637a1db9a import updated boothmul 2022-11-11 22:14:50 -05:00
Peter McGoron 45f815c5d3 changes 2022-11-11 21:57:58 -05:00
Peter McGoron 7a341a9632 yosys does not like calculated parameters 2022-10-30 15:37:45 -04:00
Peter McGoron ba901a80d7 separate math into other file 2022-10-28 17:31:23 -04:00
Peter McGoron 4f85146d61 add cycle count for each iteration 2022-10-23 14:21:31 -04:00
Peter McGoron 0a435f6dc8 rename control loop verilog simulation top level module to more descriptive name 2022-10-22 01:58:37 -04:00
Peter McGoron 7971f8ea98 change heading 2022-10-22 01:55:56 -04:00
Peter McGoron 644929ef8a move documentation to other file 2022-10-22 01:55:15 -04:00
Peter McGoron 91cbf56b02 integrate adding stored dac value into rtrunc 2022-10-22 01:52:58 -04:00
Peter McGoron f361cac01b make values update on the start of the control loop, and make resets only take effect after the control loop has completed an iteration 2022-10-21 17:38:07 -04:00
Peter McGoron 12686391ee use integer saturation for dac value adjustment 2022-10-20 19:43:13 -04:00
Peter McGoron 2a300b9438 write total value to dac, not adjustment vlaue 2022-10-20 15:42:24 -04:00
Peter McGoron c42e2fe419 add write-read interface to control loop 2022-10-18 07:10:06 -04:00
Peter McGoron dc2b1fe339 move SPI master out of control loop design 2022-10-17 14:37:37 -04:00
Peter McGoron 0ef00c15d7 move simulators to the same directory of the simulated core 2022-10-17 00:45:19 -04:00
Peter McGoron 029cc53c5f some more changes 2022-10-17 00:44:30 -04:00
Peter McGoron 5125719a1f move control loop stub code to control loop rtl 2022-10-12 08:48:34 -04:00
Peter McGoron 0298299402 add everything im working on 2022-09-16 18:01:34 -04:00
Peter McGoron 01cbcb5fae add verilog SPI 2022-07-21 17:07:52 -04:00