Commit Graph

84 Commits

Author SHA1 Message Date
Peter McGoron c8f2cf1f7a spi_switch: fix dangling else 2023-03-14 15:43:34 +00:00
Peter McGoron 90a49b6091 test and simulate spi_switch 2023-03-14 15:42:41 +00:00
Peter McGoron 36e5b964d5 lint base.v 2023-03-14 04:06:42 +00:00
Peter McGoron d198273155 add base.m4 2023-03-14 01:40:17 +00:00
Peter McGoron eadf374cd0 lint waveform.v 2023-03-10 22:59:26 +00:00
Peter McGoron 295eb8fad8 add base.v 2023-03-09 04:17:41 +00:00
Peter McGoron 89938a2ff6 move autoapproach to possibly useful waveform module: not yet tested 2023-03-03 18:30:00 +00:00
Peter McGoron 05f8878751 add submodules and switch 2023-03-03 08:06:50 +00:00
Peter McGoron 3a4224ff5b merge 2023-02-25 21:17:18 +00:00
Peter McGoron 92091d0982 stuff 2023-02-25 21:17:04 +00:00
Shell-ac 556db1f361
Add files via upload
Verilog signal propagation testbench for the intsat module
2023-01-30 14:09:49 -05:00
Peter McGoron f88e0ef15c Merge branch 'master' of ssh://github.com/phm19a/upsilon 2023-01-30 13:54:58 +00:00
Peter McGoron b3a79f41ec refactoring: move dma simulation to verilog 2023-01-30 13:54:17 +00:00
Peter McGoron 4afc655104 more refactoring 2023-01-30 13:07:34 +00:00
NickAA 822e2d4a77 Added more comments to file 2023-01-29 16:31:15 -05:00
NickAA f3e8415171 Added Menu to control_loop_sim.cpp
I was able to add the menu to the file and I fixed some bugs that came up.
For some reason the seed value (a.k.a. P value) does not accept strings or char values so I left the set_value
as is and same for the I value I don't know what the value is that is within the set_value. But everything seems
to work the way it's intended to.
2023-01-29 16:25:24 -05:00
Peter McGoron 195a9c5042 boilerplate.cpp: remove 2023-01-28 00:25:09 +00:00
Peter McGoron c7dadc5681 bram: more refactor 2023-01-27 22:58:29 +00:00
Peter McGoron 285b6d9501 refactor bram interface simulation 2023-01-27 22:27:20 +00:00
Peter McGoron c68027f24f Merge branch 'master' of ssh://github.com/phm19a/upsilon 2023-01-23 05:00:08 +00:00
Peter McGoron b1ba3434cf autoapproach: add reset test to bram 2023-01-23 04:58:38 +00:00
Peter McGoron 65b1436e0b autoapproach: test refreshing bram 2023-01-23 04:47:12 +00:00
Peter McGoron 034f76da41 autoapproach: add bram and test 2023-01-23 04:43:51 +00:00
NickAA 00ac3e03dc Added comments
I added a few comments to review what I have to change and what I need to start coding.
2023-01-20 15:24:24 -05:00
Peter McGoron 7ceaa730d9 remove hardcoded P and I changes 2023-01-12 19:19:19 +00:00
Peter McGoron 6604e35b89 autoapproach draft #1 2022-12-28 19:32:35 +00:00
Peter McGoron 96e9a3d043 raster simulate 2022-12-23 20:22:48 +00:00
Peter McGoron 013774e28b raster_sim: rewrite to fit new module definitions 2022-12-21 05:56:49 +00:00
Peter McGoron a79ace9568 raster_cmds: add 2022-12-21 05:24:33 +00:00
Peter McGoron a918d74f05 introduce control interface; pack adc_data bits into large vector instead of an array 2022-12-21 05:16:15 +00:00
Peter McGoron ac0ed9e2a7 yosys does not support input arrays 2022-12-20 06:25:45 +00:00
Peter McGoron a2acccbca6 misc 2022-12-20 06:07:54 +00:00
Peter McGoron 4ba004336c ram_shim: simulate 2022-12-20 05:51:05 +00:00
Peter McGoron 15480f11da ram_fifo: add empty and full ports 2022-12-18 06:06:44 +00:00
Peter McGoron 1be89f314c simulate and verify ram_fifo and ram_fifo_dual_port 2022-12-17 18:39:58 +00:00
Peter McGoron 60404cd026 ram_fifo.v: add simulator debugging checks 2022-12-17 10:18:15 -05:00
Peter McGoron f0f1750a9a add ram_fifo_dual_port wrapper to single port FIFO 2022-12-17 10:03:06 -05:00
Peter McGoron 3612148ee1 raster/ram_fifo: correct misspelling 2022-12-17 09:56:57 -05:00
Peter McGoron f536a41784 control_loop: remove reg keyword, yosys doesnt like it 2022-12-17 09:56:26 -05:00
Peter McGoron 644f4142a2 raster work 2022-12-17 00:46:04 +00:00
Peter McGoron ffdf4fb2f2 import Xilinx FIFO36E1 simulation 2022-12-16 20:46:00 +00:00
Peter McGoron 59b6efce7e raster_sim.v: add and lint 2022-11-26 12:00:10 -05:00
Peter McGoron a12fbf8af2 ram_shim: add and lint 2022-11-26 11:53:57 -05:00
Peter McGoron c8d7572db5 raster.v: lint 2022-11-26 11:47:06 -05:00
Peter McGoron 9282c33cce add ram shim 2022-11-24 11:07:30 -05:00
Peter McGoron 1ed48fbc90 control_loop_sim: add comments 2022-11-24 10:08:00 -05:00
Peter McGoron cef639784b control_loop_sim: modify second P value 2022-11-24 10:00:05 -05:00
Peter McGoron 1d54b41735 fix bit width bug 2022-11-24 09:55:15 -05:00
Peter McGoron 33ec8351d8 correctly (and crudely) simulate control loop
Issue was that the ADC cycle half wait (SCK delay) was too fast
for the input buffering (since MISO and MOSI are physical inputs
and not FPGA wires).
2022-11-24 09:48:19 -05:00
Peter McGoron 6ad2de97cf sketch out raster scan 2022-11-24 00:50:21 -05:00