4ba004336c
ram_shim: simulate
2022-12-20 05:51:05 +00:00
15480f11da
ram_fifo: add empty and full ports
2022-12-18 06:06:44 +00:00
1be89f314c
simulate and verify ram_fifo and ram_fifo_dual_port
2022-12-17 18:39:58 +00:00
60404cd026
ram_fifo.v: add simulator debugging checks
2022-12-17 10:18:15 -05:00
f0f1750a9a
add ram_fifo_dual_port wrapper to single port FIFO
2022-12-17 10:03:06 -05:00
3612148ee1
raster/ram_fifo: correct misspelling
2022-12-17 09:56:57 -05:00
f536a41784
control_loop: remove reg keyword, yosys doesnt like it
2022-12-17 09:56:26 -05:00
644f4142a2
raster work
2022-12-17 00:46:04 +00:00
ffdf4fb2f2
import Xilinx FIFO36E1 simulation
2022-12-16 20:46:00 +00:00
59b6efce7e
raster_sim.v: add and lint
2022-11-26 12:00:10 -05:00
a12fbf8af2
ram_shim: add and lint
2022-11-26 11:53:57 -05:00
c8d7572db5
raster.v: lint
2022-11-26 11:47:06 -05:00
9282c33cce
add ram shim
2022-11-24 11:07:30 -05:00
1ed48fbc90
control_loop_sim: add comments
2022-11-24 10:08:00 -05:00
cef639784b
control_loop_sim: modify second P value
2022-11-24 10:00:05 -05:00
1d54b41735
fix bit width bug
2022-11-24 09:55:15 -05:00
33ec8351d8
correctly (and crudely) simulate control loop
...
Issue was that the ADC cycle half wait (SCK delay) was too fast
for the input buffering (since MISO and MOSI are physical inputs
and not FPGA wires).
2022-11-24 09:48:19 -05:00
6ad2de97cf
sketch out raster scan
2022-11-24 00:50:21 -05:00
adb81e201e
fix dac simulation
2022-11-21 22:56:40 -05:00
5ff6b279b0
reverify math
2022-11-21 22:24:37 -05:00
79cae3dd66
(somewhat) fix counter
2022-11-21 22:08:25 -05:00
cfb0f92528
fix adc_sim
2022-11-21 22:04:46 -05:00
5909f548d5
control loop simulator passes lint
2022-11-21 21:41:50 -05:00
0114c449c3
correct simulation of control loop
2022-11-19 12:55:55 -05:00
a0450fb0ff
control_loop_math: fix compile errors and verify simulation
2022-11-18 19:27:29 -05:00
0c10dc921c
more work on control_loop
...
* Make SPI masters internal to control loop module
* Rename commands to use I isntead of alpha
* add ADC value -> DAC value conversion to control loop math
2022-11-18 19:11:56 -05:00
3a23ac6e92
control_loop; add dirty bit to decrease the amount of comparisons
2022-11-17 19:14:24 -05:00
8d11442cbb
update .gitignore
2022-11-17 19:07:49 -05:00
29e0e8dfb3
integrate control_loop_math into control_loop
2022-11-17 19:07:21 -05:00
d9f4a40c6d
update GUIDELINES.md
2022-11-17 18:39:48 -05:00
82ff659a44
add DAC ramp
2022-11-17 17:32:32 -05:00
0907a76c22
import spi v0.2
2022-11-14 08:43:16 -05:00
50ea679e02
Rewrite control_loop_math and simulate
...
Replace specialized math nodes with single multiplier: each constant
must be resized to fit in the multiplier. Simplifies design at the
cost of speed.
2022-11-13 18:03:55 -05:00
88c42a9f4a
add printing of fixed point values in C++
2022-11-12 01:44:30 -05:00
c21e2bbb63
add calculate dt module with simulation
2022-11-11 22:42:06 -05:00
7637a1db9a
import updated boothmul
2022-11-11 22:14:50 -05:00
45f815c5d3
changes
2022-11-11 21:57:58 -05:00
7a341a9632
yosys does not like calculated parameters
2022-10-30 15:37:45 -04:00
732be44a8d
add guidelines
2022-10-30 15:37:08 -04:00
ba901a80d7
separate math into other file
2022-10-28 17:31:23 -04:00
653040fb67
clarify licenses
2022-10-27 17:55:57 -04:00
440f144180
fixed fixed point algorithms in python
2022-10-27 17:55:12 -04:00
4f85146d61
add cycle count for each iteration
2022-10-23 14:21:31 -04:00
0a435f6dc8
rename control loop verilog simulation top level module to more descriptive name
2022-10-22 01:58:37 -04:00
7971f8ea98
change heading
2022-10-22 01:55:56 -04:00
644929ef8a
move documentation to other file
2022-10-22 01:55:15 -04:00
91cbf56b02
integrate adding stored dac value into rtrunc
2022-10-22 01:52:58 -04:00
f361cac01b
make values update on the start of the control loop, and make resets only take effect after the control loop has completed an iteration
2022-10-21 17:38:07 -04:00
12686391ee
use integer saturation for dac value adjustment
2022-10-20 19:43:13 -04:00
2a300b9438
write total value to dac, not adjustment vlaue
2022-10-20 15:42:24 -04:00
