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VexRiscv
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1028 Commits

Author SHA1 Message Date
Charles Papon 8839f8a8e9 Fix DBus AXI bridges from writePending counter deadlock 2019-11-03 16:45:24 +01:00
Charles Papon 2bf6a536c9 Fix DBus AXI bridges from writePending counter deadlock 2019-11-03 16:44:09 +01:00
Charles Papon bd2787b562 RegFilePlugin project X0 against boot glitches if no x0Init but zeroBoot 2019-11-01 16:24:07 +01:00
Charles Papon f2a5134621 Merge remote-tracking branch 'origin/rpls-mul16' 2019-10-23 22:29:35 +02:00
Charles Papon bb9261773b Fix MulDiveIterative plugin when RSx have hazard in the execute stage 2019-10-23 00:02:08 +02:00
Charles Papon 67028cdb48 Add Mul16Plugin to regression tests 
Fix missing MulSimplePlugin in regressions tests
 2019-10-21 12:53:53 +02:00
Charles Papon 8091a872f3 Fix muldiv plugin for CPU configs without memory/writeback stages 2019-10-21 12:53:03 +02:00
Richard Petri 2d56c6738c Multiplication Plugin using 16-bit DSPs 2019-10-20 22:24:19 +02:00
Charles Papon b4c75d4898 Merge remote-tracking branch 'origin/dev' into dev 2019-10-11 00:25:37 +02:00
Charles Papon a2b49ae000 Fix CFU arbitration, add CFU decoder, CFU now redirect custom-0 with func3 2019-10-11 00:25:22 +02:00
Charles Papon 310c325eaa IBusCached add Keep attribut on the line loader to avoid Artix7 block ram merge, but do not seem to have effect 2019-10-11 00:24:21 +02:00
Charles Papon 711eed1e77 MulPlugin add withInputBuffer feature and now use RSx instead of SRCx 2019-10-11 00:23:29 +02:00
Charles Papon 3fc0a74102 Add Keep attribut on dBusCached relaxedMemoryTranslationRegister feature 2019-10-11 00:22:44 +02:00
Charles Papon 51d22d4a8c Merge remote-tracking branch 'origin/cfu' into dev 2019-10-10 15:00:43 +02:00
Charles Papon 319d162f67 Merge remote-tracking branch 'origin/tigthlyCoupled' into dev 2019-10-03 12:33:27 +02:00
Charles Papon 5df56bea79 Allow getDrivingReg to properly see i$ decode.input(INSTRUCTION) register 
(used to inject instruction from the debug plugin)
 2019-10-03 00:20:33 +02:00
Charles Papon ca228a392e Merge branch 'short-pipeline-fixes' 2019-09-26 10:25:11 +02:00
Charles Papon 8d8c301662 Merge branch 'short-pipeline-fixes-xobs' into short-pipeline-fixes 2019-09-23 15:22:27 +02:00
Charles Papon 49944643d2 Add regression for data cache without writeback stage, seem to pass tests, including linux ones 2019-09-23 15:20:51 +02:00
Charles Papon bf82829e9e Data cache can now be used without writeback stage 2019-09-23 15:20:20 +02:00
Charles Papon ace963b542 Hazard on memory stage do not need to know if that's bypassable if the memory stage is the last one 2019-09-21 14:13:28 +02:00
Charles Papon e1795e59d5 Enable RF bypass on MUL DIV with pipeline wihout writeback/memory stages 2019-09-21 13:00:54 +02:00
Charles Papon e8236dfebe Add MulSimplePlugin regressions 2019-09-21 12:49:46 +02:00
Charles Papon be18d8fa5a CSR access enables are also impacted by the MMU memory access 2019-09-21 10:28:52 +02:00
Sean Cross b8b053e706 muldiviterative: fix build for short pipelines 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-20 08:36:01 +08:00
Sean Cross fdc95debef dbuscached: fix build for short pipelines 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-20 08:35:49 +08:00
Sean Cross 0b79c637b6 mulsimpleplugin: fix build for short pipelines 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-20 08:35:23 +08:00
Charles Papon fe385da850 Fix Artix7 FMax, my apologies for that, was due to a bad scripting using Kintex 7 instead 2019-09-16 14:27:41 +02:00
Charles Papon 88eb8e4e47 Fix Artix7 FMax, my apologies for that, was due to a bad scripting using Kintex 7 instead 2019-09-16 14:22:33 +02:00
Charles Papon 6ed41f7361 Improve CSR FMax 2019-09-16 13:53:55 +02:00
Charles Papon d94cee13f0 Add dummy decoding, exception code/tval 
Add Cpu generation code
Add support for always ready rsp
 2019-09-05 19:06:28 +02:00
Charles Papon 5ac443b745 Manage cases where a rsp buffer is required 2019-09-05 10:41:45 +02:00
Dolu1990 6951f5b8e6 CfuPlugin addition 2019-09-05 10:41:45 +02:00
Dolu1990 84602f89b0 Merge pull request #80 from antmicro/fix_litex_target 
Fix handling LiteX uart and timer.
 2019-09-05 10:41:45 +02:00
Dolu1990 0efcaa505d Merge pull request #79 from antmicro/litex_target 
Litex target
 2019-09-05 10:41:45 +02:00
Mateusz Holenko 86f5af5ca9 Fix handling LiteX uart and timer. 2019-09-05 10:41:45 +02:00
Charles Papon 94f1707d65 Merge branch 'dev' 2019-09-05 10:41:45 +02:00
Mateusz Holenko 8813e071bc Add `litex` target 
Use configuration from the `csr.h` file
generated dynamically when building a LiteX platform.
 2019-09-05 10:41:45 +02:00
Mateusz Holenko 64a2815544 Create makefile targets 
Allow to change build target without modifiying the sources.
In order to keep compatibilty `sim` target is built by default.
 2019-09-05 10:41:45 +02:00
Mateusz Holenko e76435c6c6 Allow to set custom DTB/OS_CALL addresses 
Setting those from command line during compilation allows
to create a custom setup without the need of modifying the
sources.
 2019-09-05 10:41:45 +02:00
Mateusz Holenko c8280a9a88 Allow to set custom RAM base address for emulator 
This is needed when loading the emulator to RAM
with an offset.
 2019-09-05 10:41:45 +02:00
Charles Papon b65ef189eb sync with SpinalHDL SDRAM changes 2019-08-29 16:03:20 +02:00
Sean Cross b91df10b21 Merge branch 'master' of github.com:SpinalHDL/VexRiscv into HEAD 2019-07-27 21:27:16 +08:00
Sean Cross b0199297fd caches: work without writeBack stage 
In the case of an MMU miss, the data caches will create a retry branch port.
These currently implicitly go into the memory/writeBack stage, however
not all CPUs have this stage.

Place the retry branch port into the correct stage.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-27 10:08:53 +08:00
Sean Cross 955e70206c MmuPlugin: fix generation without writeBack stage 
If there is no writeBack stage, the elaboration step would hit a
NullPointerException when trying to insert into the writeBack stage.

Instead, pull from the most recent stage, which is where MMU access
should reside.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-27 10:08:30 +08:00
Dolu1990 5f0c7a7faf
Merge pull request #80 from antmicro/fix_litex_target 
Fix handling LiteX uart and timer.
 2019-07-24 19:17:23 +02:00
Mateusz Holenko 5085877eed Fix handling LiteX uart and timer. 2019-07-24 16:09:21 +02:00
Dolu1990 6124ec7b14
Merge pull request #79 from antmicro/litex_target 
Litex target
 2019-07-20 02:59:42 +03:00
Mateusz Holenko 6a2584b840 Add `litex` target 
Use configuration from the `csr.h` file
generated dynamically when building a LiteX platform.
 2019-07-11 15:56:48 +02:00
Mateusz Holenko 39c3f408e5 Create makefile targets 
Allow to change build target without modifiying the sources.
In order to keep compatibilty `sim` target is built by default.
 2019-07-11 15:50:15 +02:00