Samuel Lindemer
14c39a0070
Merge remote-tracking branch 'upstream/master' into pmp
2020-12-02 14:08:32 +01:00
Samuel Lindemer
872aa19d83
Add PMP to golden model
2020-12-02 12:27:26 +01:00
Samuel Lindemer
d5b1a8f565
Add PMP test to regression suite
2020-12-01 18:38:06 +01:00
Samuel Lindemer
c5023ad973
Add PMP regression test
2020-12-01 09:10:24 +01:00
Samuel Lindemer
2d0ebf1ef5
Flush pipeline after PMP CSR writes
2020-11-25 15:38:34 +01:00
Dolu1990
e0ae46e794
Fix Csr ReadWrite interration with DBusCachedPlugin execute halt
...
# Conflicts:
# src/main/scala/vexriscv/plugin/CsrPlugin.scala
2020-11-18 14:43:24 +01:00
Samuel Lindemer
97fe279f7b
Enable PMP register lock
2020-10-29 13:37:21 +01:00
Dolu1990
dc9246715d
Do not allow jtag ebreak outside machine mode
2020-10-28 13:00:16 +01:00
Dolu1990
4209dc2792
Fix CsrPlugin privilege crossing
2020-10-28 13:00:15 +01:00
Samuel Lindemer
fc2c8a7c37
Initial commit of PMP plugin
2020-10-27 09:38:58 +01:00
Marcus Comstedt
6c8e97f825
Update big endian instruction encoding
...
Between draft-20181101-ebe1ca4 and draft-20190622-6993896 of the
RISC-V Instruction Set Manual, the wording was changed from requiring
"natural endianness" of instruction parcels to require them to be
little endian.
Update the big endian instruction pipe to reflect the newer requirement.
2020-10-20 18:05:31 +02:00
Dolu1990
98de02051e
Merge pull request #135 from zeldin/bigendian
...
Add support for big endian byte ordering
2020-10-01 16:43:00 +02:00
Marcus Comstedt
8e466dd13c
Add support for RV32E in RegFilePlugin
...
The RV32E extension removes registers x16-x31 from the ISA. This
is useful when compiling with -mem2reg to save on BRAMs. On iCE40
HX8K this option saves 1285 LC:s, which also improves the routing
situation, when using -mem2reg.
Note that the illegal instruction exception required by the RV32E
specification for accesses to registers x16-x31 is not implemented.
2020-09-06 17:05:31 +02:00
Marcus Comstedt
c489143442
Add support for big endian byte ordering
2020-08-30 15:17:09 +02:00
Dolu1990
2942d0652a
fix Briey verilator
2020-06-01 11:18:25 +02:00
Tom Verbeure
b901651ab5
Add default value of NONE to uinstret CSR.
2020-05-19 14:48:35 -07:00
Tom Verbeure
c74b03b4de
Add uinstret support.
2020-05-19 13:40:46 -07:00
Dolu1990
ddc59bc404
Fix DebugPlugin step by step
2020-04-07 12:27:52 +02:00
Dolu1990
97258c214a
Merge pull request #115 from antmicro/fix_emulator
...
emulator: Use external hw/common.h from LiteX
2020-03-18 12:02:27 +01:00
Dolu1990
defe3c5558
DataCache relax flush timings
2020-03-08 12:35:24 +01:00
Dolu1990
97db4f02a0
Merge branch 'rework_fetch' into dev
2020-03-07 18:22:46 +01:00
Dolu1990
44005ebf31
update Synthesis results
2020-03-07 18:22:01 +01:00
Charles Papon
58af94269e
add CsrPlugin.csrOhDecoder
2020-03-05 00:13:04 +01:00
Charles Papon
505d0b700a
MulDivPlugin now give names to div stages
2020-03-04 19:58:54 +01:00
Dolu1990
0a212c91fd
update synthesisBench paths
2020-03-04 18:13:56 +01:00
Dolu1990
ff5cfc0dde
Fix DebugPlugin step
2020-03-03 18:27:53 +01:00
Dolu1990
12463e40a4
improve debugPlugin step logic
2020-03-03 15:59:30 +01:00
Dolu1990
ef5398ce21
Fix #117 DataCache mem blackboxing
2020-03-02 14:24:27 +01:00
Dolu1990
54581f6d9e
Fix #117 DataCache mem blackboxing
2020-03-02 14:23:59 +01:00
Dolu1990
78d4660282
Merge branch 'dev' into rework_fetch
...
# Conflicts:
# src/test/scala/vexriscv/TestIndividualFeatures.scala
2020-03-01 22:58:25 +01:00
Dolu1990
ea5464ea26
TestIndividualFeatures is now multithreaded
2020-03-01 21:40:53 +01:00
Dolu1990
559260020b
Improve testing infrastructure with more options and better readme
...
https://github.com/litex-hub/linux-on-litex-vexriscv/issues/112
2020-03-01 13:02:08 +01:00
Charles Papon
25d880f6c7
Fix synthesis bench
2020-02-28 18:20:08 +01:00
Charles Papon
c94d8f1c6c
Fetcher and IBusSimplePlugin flush reworked
2020-02-28 17:23:44 +01:00
Charles Papon
492310e6fa
DBusCachedPlugin fix noWriteBack redo priority
2020-02-28 17:21:59 +01:00
Charles Papon
76d063f20a
Fix MulPlugin keep attribute
2020-02-24 22:43:08 +01:00
Mateusz Holenko
f88b259eba
emulator: Use external hw/common.h from LiteX
...
Remove code copied from `hw/common.h` and use
the header from the LiteX repository provided
using `LITEX_BASE` environment variable.
Content of `common.h` is now evolving (new functions
are added, some are removed) and syncing it
between repos would be cumbersome.
2020-02-24 14:27:45 +01:00
Charles Papon
485b4a5838
Improve maxPerf configs
2020-02-23 23:52:43 +01:00
Charles Papon
fad09e805f
Add Fetcher.predictionBuffer option to pipeline BRANCH_TARGET, higher FMax, about 1 ns critical path gain on Arty7 => 5 ns
2020-02-23 23:18:27 +01:00
Charles Papon
67d2071a32
typo
2020-02-23 23:17:02 +01:00
Charles Papon
c8016e90a4
MulPlugin now add KEEP attribute on RS1 and RS2 to force Vivado to not retime it with the DSP
2020-02-23 20:25:31 +01:00
Charles Papon
01e5112680
Fetcher RVC ensure redo keep PC(1)
...
Fix BranchTarget RVC inibition
2020-02-23 10:44:44 +01:00
Charles Papon
5ea0b57d1b
Fix BRANCH_TARGET with RVC patch
2020-02-22 11:53:47 +01:00
Charles Papon
41008551c1
CsrPlugin redo interface do not need next pc calculation
2020-02-21 20:01:35 +01:00
Charles Papon
4ad1215873
Fix iBusSimplePlugin MMU integration
2020-02-21 13:28:42 +01:00
Charles Papon
befc54a444
No more Fetcher flush() API as it can now be done via the decoder.flushNext
2020-02-21 13:28:29 +01:00
Charles Papon
32fade50e5
Fix fetcher decompressor when driving decode stage
2020-02-21 02:03:29 +01:00
Charles Papon
59508d5b57
Fix target branch prediction for RVC, all default configs pass dhrystone
2020-02-20 02:27:57 +01:00
Charles Papon
a684d5e4d1
Rework/clean decompressor logic
2020-02-19 01:20:52 +01:00
Charles Papon
a7440426fd
Fix FetchPlugin redo gen condition
...
Fix injectorFailure reset
2020-02-18 01:00:11 +01:00
