Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
942 Commits 39 Branches 2 Tags 15 MiB
Commit Graph

942 Commits

Author SHA1 Message Date
Samuel Lindemer 2d0ebf1ef5 Flush pipeline after PMP CSR writes 2020-11-25 15:38:34 +01:00
Samuel Lindemer 97fe279f7b Enable PMP register lock 2020-10-29 13:37:21 +01:00
Samuel Lindemer fc2c8a7c37 Initial commit of PMP plugin 2020-10-27 09:38:58 +01:00
Dolu1990 d490f903ea
Merge pull request #145 from zeldin/bigendian2 
Update big endian instruction encoding
 2020-10-21 12:56:56 +02:00
Marcus Comstedt 6c8e97f825 Update big endian instruction encoding 
Between draft-20181101-ebe1ca4 and draft-20190622-6993896 of the
RISC-V Instruction Set Manual, the wording was changed from requiring
"natural endianness" of instruction parcels to require them to be
little endian.

Update the big endian instruction pipe to reflect the newer requirement.
 2020-10-20 18:05:31 +02:00
Dolu1990 98de02051e
Merge pull request #135 from zeldin/bigendian 
Add support for big endian byte ordering
 2020-10-01 16:43:00 +02:00
Dolu1990 9d35e75fb5
Update README.md 2020-10-01 16:41:24 +02:00
Dolu1990 775b336ee0
Merge pull request #136 from zeldin/rv32e 
Add support for RV32E in RegFilePlugin
 2020-09-06 22:23:24 +02:00
Marcus Comstedt 8e466dd13c Add support for RV32E in RegFilePlugin 
The RV32E extension removes registers x16-x31 from the ISA.  This
is useful when compiling with -mem2reg to save on BRAMs.  On iCE40
HX8K this option saves 1285 LC:s, which also improves the routing
situation, when using -mem2reg.

Note that the illegal instruction exception required by the RV32E
specification for accesses to registers x16-x31 is not implemented.
 2020-09-06 17:05:31 +02:00
Marcus Comstedt c489143442 Add support for big endian byte ordering 2020-08-30 15:17:09 +02:00
Dolu1990 2942d0652a fix Briey verilator 2020-06-01 11:18:25 +02:00
Dolu1990 24b676ce30
Merge pull request #124 from tomverbeure/uinstret 
Add uinstret support.
 2020-05-20 10:35:42 +02:00
Tom Verbeure b901651ab5 Add default value of NONE to uinstret CSR. 2020-05-19 14:48:35 -07:00
Tom Verbeure c74b03b4de Add uinstret support. 2020-05-19 13:40:46 -07:00
Dolu1990 ddc59bc404 Fix DebugPlugin step by step 2020-04-07 12:27:52 +02:00
Dolu1990 31d2aaa05b
Update README.md 2020-03-28 15:38:32 +01:00
Dolu1990 31667b18d8
Update README.md 2020-03-20 11:26:38 +01:00
Dolu1990 97258c214a
Merge pull request #115 from antmicro/fix_emulator 
emulator: Use external hw/common.h from LiteX
 2020-03-18 12:02:27 +01:00
Dolu1990 95237b23ea SpinalHDL 1.4.0 
Merge branch 'dev'
 2020-03-09 13:49:06 +01:00
Dolu1990 ab2f4cd2b7 Merge branch 'master' into dev 
# Conflicts:
#	README.md
#	build.sbt
 2020-03-09 13:41:23 +01:00
Dolu1990 5f90702b2f SpinalHDL update 2020-03-09 13:14:16 +01:00
Dolu1990 defe3c5558 DataCache relax flush timings 2020-03-08 12:35:24 +01:00
Dolu1990 04bf1a4ced Fix build.sbt 2020-03-08 00:23:19 +01:00
Dolu1990 7a5afb86a5 Fix build.sbt 2020-03-07 19:09:33 +01:00
Dolu1990 97db4f02a0 Merge branch 'rework_fetch' into dev 2020-03-07 18:22:46 +01:00
Dolu1990 44005ebf31 update Synthesis results 2020-03-07 18:22:01 +01:00
Charles Papon 2c6076ba97 improve smp spec 2020-03-07 13:35:21 +01:00
Charles Papon b7ae902bbc smp spec improvements, no more read abort 2020-03-05 00:14:11 +01:00
Charles Papon 58af94269e add CsrPlugin.csrOhDecoder 2020-03-05 00:13:04 +01:00
Charles Papon 50ec0a1917 update readme perf 2020-03-05 00:12:46 +01:00
Charles Papon 505d0b700a MulDivPlugin now give names to div stages 2020-03-04 19:58:54 +01:00
Dolu1990 0a212c91fd update synthesisBench paths 2020-03-04 18:13:56 +01:00
Dolu1990 ff5cfc0dde Fix DebugPlugin step 2020-03-03 18:27:53 +01:00
Dolu1990 12463e40a4 improve debugPlugin step logic 2020-03-03 15:59:30 +01:00
Charles Papon fd37962a58 typo 2020-03-03 10:56:12 +01:00
Dolu1990 ef5398ce21 Fix #117 DataCache mem blackboxing 2020-03-02 14:24:27 +01:00
Dolu1990 54581f6d9e Fix #117 DataCache mem blackboxing 2020-03-02 14:23:59 +01:00
Dolu1990 78d4660282 Merge branch 'dev' into rework_fetch 
# Conflicts:
#	src/test/scala/vexriscv/TestIndividualFeatures.scala
 2020-03-01 22:58:25 +01:00
Dolu1990 ea5464ea26 TestIndividualFeatures is now multithreaded 2020-03-01 21:40:53 +01:00
Dolu1990 02545b9bea typo 2020-03-01 13:03:40 +01:00
Dolu1990 559260020b Improve testing infrastructure with more options and better readme 
https://github.com/litex-hub/linux-on-litex-vexriscv/issues/112
 2020-03-01 13:02:08 +01:00
Dolu1990 0c7556ad7f
Update README.md 2020-02-29 23:46:21 +01:00
Charles Papon 25d880f6c7 Fix synthesis bench 2020-02-28 18:20:08 +01:00
Charles Papon c94d8f1c6c Fetcher and IBusSimplePlugin flush reworked 2020-02-28 17:23:44 +01:00
Charles Papon 492310e6fa DBusCachedPlugin fix noWriteBack redo priority 2020-02-28 17:21:59 +01:00
Charles Papon 76d063f20a Fix MulPlugin keep attribute 2020-02-24 22:43:08 +01:00
Mateusz Holenko f88b259eba emulator: Use external hw/common.h from LiteX 
Remove code copied from `hw/common.h` and use
the header from the LiteX repository provided
using `LITEX_BASE` environment variable.

Content of `common.h` is now evolving (new functions
are added, some are removed) and syncing it
between repos would be cumbersome.
 2020-02-24 14:27:45 +01:00
Charles Papon 999a868c14 Update readme VexRiscv perf numbers 2020-02-24 00:07:14 +01:00
Charles Papon 485b4a5838 Improve maxPerf configs 2020-02-23 23:52:43 +01:00
Charles Papon fad09e805f Add Fetcher.predictionBuffer option to pipeline BRANCH_TARGET, higher FMax, about 1 ns critical path gain on Arty7 => 5 ns 2020-02-23 23:18:27 +01:00