Hardware/VexRiscv
1
0
Fork 0
mirror of https://github.com/SpinalHDL/VexRiscv.git synced 2025-01-03 03:43:39 -05:00
Code Issues Projects Releases Packages Wiki Activity
1345 commits 39 branches 2 tags 15 MiB
Commit graph

1345 commits

This branch
This branch
All branches
Author SHA1 Message Date
Dolu1990
636d53cf63 fpu now track commits using a counter per pipeline per port 2021-03-02 16:13:12 +01:00
Dolu1990
81c193af1f Improve subnormal/normal rounding 2021-02-26 16:32:42 +01:00
Dolu1990
de81da36eb Fpu fix a few div special cases 2021-02-25 19:39:57 +01:00
Dolu1990
de09ed3fcb fpu added exact div/sqrt implementations using iterative approaches 2021-02-25 15:28:38 +01:00
Dolu1990
be81cc1e0e CfuPlugin.response_ok removed 2021-02-23 12:23:48 +01:00
Dolu1990
47673863fb fpu test cleaning 2021-02-22 19:27:55 +01:00
Dolu1990
b1f4c06d4e fpu fix arbitration/lock bugs 
add getVexRiscvRegressionArgs
 2021-02-22 19:27:26 +01:00
Dolu1990
a6e89fe05c fpu vex regression goldenModel can now assert FPU interface 2021-02-19 17:55:56 +01:00
Dolu1990
3f226b758c fpu fix exception flag handeling 2021-02-19 13:03:48 +01:00
Dolu1990
e504afbf18 fpu integration wip, got mandelbrot to work in linux with no inline (crash when inlined) 2021-02-19 11:26:28 +01:00
Dolu1990
8537d18b16 fpu improve fmax 2021-02-17 16:35:52 +01:00
Dolu1990
1e647f799c fpu Fix VexRiscv integration and add software f64 tests (pass) 2021-02-17 12:33:27 +01:00
Dolu1990
06b7a91de4 MulPlugin fix buffer interraction with partial regfile bypass 2021-02-17 11:35:17 +01:00
Dolu1990
f180ba2fc9 fpu double fixes 
DataCache now support wide load/store
 2021-02-16 15:38:51 +01:00
Dolu1990
8b2a2afb6f VexRIscvSmpCluster add options 2021-02-16 14:42:31 +01:00
Dolu1990
1752b9e6d6 DataCache.toBmb with aggregation sync path pipelined 2021-02-16 14:17:21 +01:00
Dolu1990
fe690528f7 MulPlugin.outputBuffer feature added 2021-02-16 14:16:57 +01:00
Dolu1990
3b99090879 VexRiscvConfig.get added 2021-02-16 14:15:20 +01:00
Dolu1990
7d3b35c32c fpu f64/f32 pass all tests 2021-02-12 14:48:44 +01:00
Dolu1990
9a25a12879 fpu add FCVT_X_X 2021-02-11 17:40:35 +01:00
Dolu1990
82dfd10dba fpu fix f32 tests for f64 fpu 2021-02-11 16:42:17 +01:00
Dolu1990
b6eda1ad7a fpu f64 load/store/mv/mul seems ok 2021-02-11 16:07:47 +01:00
Dolu1990
e97c2de837 fpu f64 wip 2021-02-10 19:27:26 +01:00
Dolu1990
88dffc21f7 fpu f64 wip 2021-02-10 13:20:17 +01:00
Dolu1990
889cc5fde2 fpu refractoring 2021-02-10 12:16:56 +01:00
Dolu1990
1fe993ad10 fpu fixed corner cases, FpuPlugin coupling, pass rv-test excepted div (accuracy), can run C sinf successfully 2021-02-09 18:35:47 +01:00
Dolu1990
bf6a64b6b5 fpu sgnj / fclass / fmv pass 2021-02-08 15:29:50 +01:00
Dolu1990
bf0829231d fpu min max pass 2021-02-06 14:08:21 +01:00
Dolu1990
008fadeaa9 fpu eq lt le pass testfloat 2021-02-06 13:20:27 +01:00
Dolu1990
6170243283 fpu got exception flag right for add/sub/mul/i2f/f2i 2021-02-05 16:24:14 +01:00
Dolu1990
f278900cbe VexRiscvSmpCluster can now set regfile read kind 2021-02-05 11:09:18 +01:00
Dolu1990
0f1ca72171 fix synthesis bench 2021-02-04 12:43:31 +01:00
Dolu1990
936e5823dc fpu test wip 2021-02-04 12:41:49 +01:00
Dolu1990
3710fd3492 fix synthesis bench 2021-02-04 12:41:31 +01:00
Dolu1990
02b5b9b05c fpu load subnormal and i2f now use single cycle shifter 2021-02-03 16:48:09 +01:00
Dolu1990
8e7e736e3e Merge branch 'dev' into fpu 
# Conflicts:
#	src/main/scala/vexriscv/Riscv.scala
#	src/main/scala/vexriscv/ip/fpu/FpuCore.scala
#	src/main/scala/vexriscv/ip/fpu/Interface.scala
#	src/test/scala/vexriscv/ip/fpu/FpuTest.scala
 2021-02-03 16:06:17 +01:00
Dolu1990
8eb8356dea fpu wip 2021-02-03 14:28:02 +01:00
Dolu1990
1d0eecdcb0 fpu f2i rounding ok and full shifter 2021-02-03 14:27:52 +01:00
Dolu1990
ef011fa0d4 fpu moved 1 bit from round to mantissa 2021-02-02 11:29:35 +01:00
Dolu1990
a87cb202b1 fpu i2f rounding ok 2021-02-01 16:12:38 +01:00
Dolu1990
d92adfbad0 SpinalHDL version++ 2021-02-01 15:20:57 +01:00
Dolu1990
6ee45a1014 SpinalHDL version++ 2021-02-01 12:28:33 +01:00
Dolu1990
36b3cd9188 Merge branch 'dev' 2021-02-01 12:19:21 +01:00
Dolu1990
98eaeaabc8
fix regression.mk typo 2021-01-30 22:34:54 -01:00
Dolu1990
6aa6191240 Merge branch 'master' into dev 
# Conflicts:
#	build.sbt
#	src/main/scala/vexriscv/Riscv.scala
#	src/main/scala/vexriscv/ip/DataCache.scala
#	src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
#	src/main/scala/vexriscv/plugin/MmuPlugin.scala
#	src/test/cpp/regression/makefile
#	src/test/scala/vexriscv/TestIndividualFeatures.scala
 2021-01-30 20:30:21 +01:00
Dolu1990
c51b0fcafe fpu mul now pass all roundings 2021-01-29 22:30:19 +01:00
Dolu1990
0997592768 fpu mul sems all good excepted subnormal rounding 2021-01-29 16:13:49 +01:00
Dolu1990
3c4df1e963 fpu moved overflow rounding to writeback 2021-01-29 14:37:52 +01:00
Dolu1990
fc3e6a6d0a fpu add rounding is ok excepted infinity result 2021-01-28 20:26:43 +01:00
Dolu1990
1ae84ea83b fpu added proper rounding for add (need to manage substraction) 2021-01-28 00:25:16 +01:00