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VexRiscv
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963 Commits

Author SHA1 Message Date
Dolu1990 50a69d8d4a
Merge pull request #163 from lindemer/pmp-warl 
Make all PMP registers WARL according to specification
 2021-01-21 10:50:49 +01:00
Samuel Lindemer 6c13e6458f Remove registers storing PMP region bounds 2021-01-20 14:27:38 +01:00
Samuel Lindemer 828ea96006 PMP registers are now WARL 2021-01-20 09:27:35 +01:00
Dolu1990 ed68c8cf04
Merge pull request #162 from lindemer/paging 
Distinguish between page faults from MMU and access faults from PMP
 2021-01-18 22:18:06 +01:00
Samuel Lindemer 5e6c645461 Distinguish between page faults from MMU and access faults from PMP 2021-01-14 09:45:38 +01:00
Dolu1990 d2855fcfca
Merge pull request #147 from lindemer/pmp 
Physical Memory Protection (PMP) plugin
 2020-12-11 15:22:28 +01:00
Samuel Lindemer 7d699dcc13 Remove PMP from MachineOs test defaults 2020-12-10 09:42:27 +01:00
Samuel Lindemer f2ce2eab00 PMP plugin passes regression tests 2020-12-07 12:04:45 +01:00
Samuel Lindemer 763eebeeba Add TOR support, tests pass on GenZephyr 2020-12-04 17:13:31 +01:00
Samuel Lindemer 5cb5061d9b PMP passes test with GenZephyr, but pipeline flushes have been disabled 2020-12-03 17:29:31 +01:00
Samuel Lindemer 987de8fb6a Lock PMP address registers in golden model 2020-12-02 14:18:17 +01:00
Samuel Lindemer 14c39a0070 Merge remote-tracking branch 'upstream/master' into pmp 2020-12-02 14:08:32 +01:00
Samuel Lindemer 872aa19d83 Add PMP to golden model 2020-12-02 12:27:26 +01:00
Samuel Lindemer d5b1a8f565 Add PMP test to regression suite 2020-12-01 18:38:06 +01:00
Samuel Lindemer c5023ad973 Add PMP regression test 2020-12-01 09:10:24 +01:00
Dolu1990 1b65a9e523
remove libts-dev from readme 2020-11-30 16:11:00 +01:00
Samuel Lindemer 2d0ebf1ef5 Flush pipeline after PMP CSR writes 2020-11-25 15:38:34 +01:00
Dolu1990 e0ae46e794 Fix Csr ReadWrite interration with DBusCachedPlugin execute halt 
# Conflicts:
#	src/main/scala/vexriscv/plugin/CsrPlugin.scala
 2020-11-18 14:43:24 +01:00
Dolu1990 dae633aa7d
Merge pull request #150 from banahogg/patch-1 
Update GCC prebuild instructions for sifive.com reorg
 2020-11-15 11:25:50 +01:00
banahogg d1691e9478
Update GCC prebuild instructions for sifive.com reorg 2020-11-14 17:31:50 -08:00
Samuel Lindemer 97fe279f7b Enable PMP register lock 2020-10-29 13:37:21 +01:00
Dolu1990 dc9246715d Do not allow jtag ebreak outside machine mode 2020-10-28 13:00:16 +01:00
Dolu1990 4209dc2792 Fix CsrPlugin privilege crossing 2020-10-28 13:00:15 +01:00
Samuel Lindemer fc2c8a7c37 Initial commit of PMP plugin 2020-10-27 09:38:58 +01:00
Dolu1990 d490f903ea
Merge pull request #145 from zeldin/bigendian2 
Update big endian instruction encoding
 2020-10-21 12:56:56 +02:00
Marcus Comstedt 6c8e97f825 Update big endian instruction encoding 
Between draft-20181101-ebe1ca4 and draft-20190622-6993896 of the
RISC-V Instruction Set Manual, the wording was changed from requiring
"natural endianness" of instruction parcels to require them to be
little endian.

Update the big endian instruction pipe to reflect the newer requirement.
 2020-10-20 18:05:31 +02:00
Dolu1990 98de02051e
Merge pull request #135 from zeldin/bigendian 
Add support for big endian byte ordering
 2020-10-01 16:43:00 +02:00
Dolu1990 9d35e75fb5
Update README.md 2020-10-01 16:41:24 +02:00
Dolu1990 775b336ee0
Merge pull request #136 from zeldin/rv32e 
Add support for RV32E in RegFilePlugin
 2020-09-06 22:23:24 +02:00
Marcus Comstedt 8e466dd13c Add support for RV32E in RegFilePlugin 
The RV32E extension removes registers x16-x31 from the ISA.  This
is useful when compiling with -mem2reg to save on BRAMs.  On iCE40
HX8K this option saves 1285 LC:s, which also improves the routing
situation, when using -mem2reg.

Note that the illegal instruction exception required by the RV32E
specification for accesses to registers x16-x31 is not implemented.
 2020-09-06 17:05:31 +02:00
Marcus Comstedt c489143442 Add support for big endian byte ordering 2020-08-30 15:17:09 +02:00
Dolu1990 2942d0652a fix Briey verilator 2020-06-01 11:18:25 +02:00
Dolu1990 24b676ce30
Merge pull request #124 from tomverbeure/uinstret 
Add uinstret support.
 2020-05-20 10:35:42 +02:00
Tom Verbeure b901651ab5 Add default value of NONE to uinstret CSR. 2020-05-19 14:48:35 -07:00
Tom Verbeure c74b03b4de Add uinstret support. 2020-05-19 13:40:46 -07:00
Dolu1990 ddc59bc404 Fix DebugPlugin step by step 2020-04-07 12:27:52 +02:00
Dolu1990 31d2aaa05b
Update README.md 2020-03-28 15:38:32 +01:00
Dolu1990 31667b18d8
Update README.md 2020-03-20 11:26:38 +01:00
Dolu1990 97258c214a
Merge pull request #115 from antmicro/fix_emulator 
emulator: Use external hw/common.h from LiteX
 2020-03-18 12:02:27 +01:00
Dolu1990 95237b23ea SpinalHDL 1.4.0 
Merge branch 'dev'
 2020-03-09 13:49:06 +01:00
Dolu1990 ab2f4cd2b7 Merge branch 'master' into dev 
# Conflicts:
#	README.md
#	build.sbt
 2020-03-09 13:41:23 +01:00
Dolu1990 5f90702b2f SpinalHDL update 2020-03-09 13:14:16 +01:00
Dolu1990 defe3c5558 DataCache relax flush timings 2020-03-08 12:35:24 +01:00
Dolu1990 04bf1a4ced Fix build.sbt 2020-03-08 00:23:19 +01:00
Dolu1990 7a5afb86a5 Fix build.sbt 2020-03-07 19:09:33 +01:00
Dolu1990 97db4f02a0 Merge branch 'rework_fetch' into dev 2020-03-07 18:22:46 +01:00
Dolu1990 44005ebf31 update Synthesis results 2020-03-07 18:22:01 +01:00
Charles Papon 2c6076ba97 improve smp spec 2020-03-07 13:35:21 +01:00
Charles Papon b7ae902bbc smp spec improvements, no more read abort 2020-03-05 00:14:11 +01:00
Charles Papon 58af94269e add CsrPlugin.csrOhDecoder 2020-03-05 00:13:04 +01:00