Dolu1990
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341c159d06
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data cache relax assert into error
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2021-03-15 14:43:22 +01:00 |
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Dolu1990
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3a34b8dae2
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Merge branch 'dev' into fiber
# Conflicts:
# src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
# src/main/scala/vexriscv/plugin/MulPlugin.scala
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2021-03-15 10:35:02 +01:00 |
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Charles Papon
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ff4e5e4666
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wipe generator
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2021-03-11 18:02:02 +01:00 |
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Charles Papon
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adc37b269c
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FpuPlugin.pending is now 6 bits
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2021-03-11 13:06:50 +01:00 |
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Charles Papon
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845cfcb966
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DebugPlugin.fromBscane2 added
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2021-03-10 20:35:44 +01:00 |
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Charles Papon
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67d2f72a4b
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fiber sync
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2021-03-07 20:43:02 +01:00 |
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Dolu1990
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75bbb28ef6
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readme update verlator version
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2021-03-06 19:49:23 +01:00 |
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Dolu1990
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e384bfe145
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fiber update
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2021-03-05 22:04:20 +01:00 |
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Dolu1990
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fd234bbf9e
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fix cfu gen error
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2021-03-05 09:41:05 +01:00 |
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Dolu1990
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aee8841438
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CFU ensure that CFU_IN_FLIGHT do not produce false positive when the pipeline is stuck
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2021-03-05 09:41:05 +01:00 |
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Dolu1990
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ec507308e7
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fix cfu gen error
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2021-03-04 20:29:33 +01:00 |
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Dolu1990
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bdc52097b6
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CFU ensure that CFU_IN_FLIGHT do not produce false positive when the pipeline is stuck
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2021-03-04 20:15:01 +01:00 |
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Dolu1990
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0530d22a1d
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sync
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2021-03-04 16:06:18 +01:00 |
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Dolu1990
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caf1bde49b
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Add MuraxAsicBlackBox example
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2021-03-04 10:16:45 +01:00 |
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Dolu1990
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4bdab667cc
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fpu fix cmd / commit race condition
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2021-03-02 19:39:55 +01:00 |
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Dolu1990
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636d53cf63
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fpu now track commits using a counter per pipeline per port
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2021-03-02 16:13:12 +01:00 |
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Dolu1990
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81c193af1f
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Improve subnormal/normal rounding
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2021-02-26 16:32:42 +01:00 |
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Dolu1990
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de81da36eb
|
Fpu fix a few div special cases
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2021-02-25 19:39:57 +01:00 |
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Dolu1990
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de09ed3fcb
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fpu added exact div/sqrt implementations using iterative approaches
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2021-02-25 15:28:38 +01:00 |
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Dolu1990
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be81cc1e0e
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CfuPlugin.response_ok removed
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2021-02-23 12:23:48 +01:00 |
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Dolu1990
|
47673863fb
|
fpu test cleaning
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2021-02-22 19:27:55 +01:00 |
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Dolu1990
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b1f4c06d4e
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fpu fix arbitration/lock bugs
add getVexRiscvRegressionArgs
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2021-02-22 19:27:26 +01:00 |
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Dolu1990
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a6e89fe05c
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fpu vex regression goldenModel can now assert FPU interface
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2021-02-19 17:55:56 +01:00 |
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Dolu1990
|
3f226b758c
|
fpu fix exception flag handeling
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2021-02-19 13:03:48 +01:00 |
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Dolu1990
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e504afbf18
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fpu integration wip, got mandelbrot to work in linux with no inline (crash when inlined)
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2021-02-19 11:26:28 +01:00 |
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Dolu1990
|
8537d18b16
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fpu improve fmax
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2021-02-17 16:35:52 +01:00 |
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Dolu1990
|
1e647f799c
|
fpu Fix VexRiscv integration and add software f64 tests (pass)
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2021-02-17 12:33:27 +01:00 |
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Dolu1990
|
06b7a91de4
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MulPlugin fix buffer interraction with partial regfile bypass
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2021-02-17 11:35:17 +01:00 |
|
Dolu1990
|
f180ba2fc9
|
fpu double fixes
DataCache now support wide load/store
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2021-02-16 15:38:51 +01:00 |
|
Dolu1990
|
8b2a2afb6f
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VexRIscvSmpCluster add options
|
2021-02-16 14:42:31 +01:00 |
|
Dolu1990
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1752b9e6d6
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DataCache.toBmb with aggregation sync path pipelined
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2021-02-16 14:17:21 +01:00 |
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Dolu1990
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fe690528f7
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MulPlugin.outputBuffer feature added
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2021-02-16 14:16:57 +01:00 |
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Dolu1990
|
3b99090879
|
VexRiscvConfig.get added
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2021-02-16 14:15:20 +01:00 |
|
Dolu1990
|
7d3b35c32c
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fpu f64/f32 pass all tests
|
2021-02-12 14:48:44 +01:00 |
|
Dolu1990
|
9a25a12879
|
fpu add FCVT_X_X
|
2021-02-11 17:40:35 +01:00 |
|
Dolu1990
|
82dfd10dba
|
fpu fix f32 tests for f64 fpu
|
2021-02-11 16:42:17 +01:00 |
|
Dolu1990
|
b6eda1ad7a
|
fpu f64 load/store/mv/mul seems ok
|
2021-02-11 16:07:47 +01:00 |
|
Dolu1990
|
e97c2de837
|
fpu f64 wip
|
2021-02-10 19:27:26 +01:00 |
|
Dolu1990
|
88dffc21f7
|
fpu f64 wip
|
2021-02-10 13:20:17 +01:00 |
|
Dolu1990
|
889cc5fde2
|
fpu refractoring
|
2021-02-10 12:16:56 +01:00 |
|
Dolu1990
|
1fe993ad10
|
fpu fixed corner cases, FpuPlugin coupling, pass rv-test excepted div (accuracy), can run C sinf successfully
|
2021-02-09 18:35:47 +01:00 |
|
Dolu1990
|
bf6a64b6b5
|
fpu sgnj / fclass / fmv pass
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2021-02-08 15:29:50 +01:00 |
|
Dolu1990
|
bf0829231d
|
fpu min max pass
|
2021-02-06 14:08:21 +01:00 |
|
Dolu1990
|
008fadeaa9
|
fpu eq lt le pass testfloat
|
2021-02-06 13:20:27 +01:00 |
|
Dolu1990
|
6170243283
|
fpu got exception flag right for add/sub/mul/i2f/f2i
|
2021-02-05 16:24:14 +01:00 |
|
Dolu1990
|
f278900cbe
|
VexRiscvSmpCluster can now set regfile read kind
|
2021-02-05 11:09:18 +01:00 |
|
Dolu1990
|
0f1ca72171
|
fix synthesis bench
|
2021-02-04 12:43:31 +01:00 |
|
Dolu1990
|
936e5823dc
|
fpu test wip
|
2021-02-04 12:41:49 +01:00 |
|
Dolu1990
|
3710fd3492
|
fix synthesis bench
|
2021-02-04 12:41:31 +01:00 |
|
Dolu1990
|
02b5b9b05c
|
fpu load subnormal and i2f now use single cycle shifter
|
2021-02-03 16:48:09 +01:00 |