77e361e91e
Merge branch 'dev'
2022-02-05 12:08:43 +01:00
5714680278
Merge branch 'master' into dev
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# Conflicts:
# build.sbt
2022-02-05 11:32:40 +01:00
62c07670af
version++
2022-02-05 11:31:04 +01:00
4dd650736f
verilator++
2022-02-04 16:36:11 +01:00
378c0f8723
verilator++
2022-02-04 16:20:43 +01:00
8b2f107d46
verilator++
2022-02-04 15:10:57 +01:00
7d9a50357f
Merge pull request #233 from dnltz/WIP/dnltz/csr-registers
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plugin: CsrPlugin: Init cycle and instret registers
2022-01-27 12:05:43 +01:00
57dd80a566
plugin: CsrPlugin: Init cycle and instret registers
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Both counters are initialized with "randBoot()". This is fine for FPGA
designs because the registers can be loaded with default values but
ASIC designs require to load the value during a reset.
Since both counters require to start at 0 (read-only CSR registers),
change both registers from "randBoot()" to "init(0)".
Error:
reg [63:0] CsrPlugin_mcycle = 64'b0000000...00000000000;
|
Warning : Ignoring unsynthesizable construct. [VLOGPT-37]
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
2022-01-26 08:59:03 +01:00
9c34a1fd2e
updated related to JtagInstructionWrapper.ignoreWidth
2022-01-14 09:59:24 +01:00
b8e904e43f
syncronize golden model with dut for lrsc reservation
2022-01-10 19:55:28 +01:00
6e77f32087
sim golden model lrsc reservation sync
2022-01-10 16:08:38 +01:00
da53de360f
Fix lrsc from last commit
2022-01-10 14:21:20 +01:00
f46ad43f39
DataCache.withInternalLrSc reserved clearing fix
2022-01-10 13:39:41 +01:00
349993b235
Merge pull request #230 from OscarShiang/typo
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Fix typo in Linux.scala
2022-01-04 11:02:27 +01:00
fe6c391fe4
Fix typo in Linux.scala
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Correct "machime" to "machine".
2022-01-04 16:31:23 +08:00
34e5cafb75
Enable scala 2.13 compatibility
2021-12-20 09:38:35 +01:00
4824827b7e
Enable scala 2.13 compatibility
2021-12-20 09:38:02 +01:00
a340798840
Update build.properties
2021-12-18 09:11:08 +01:00
53a3330340
Update build.properties
2021-12-18 09:10:43 +01:00
dd12047aa7
Merge branch dev (SpinalHDL 1.6.1)
2021-12-15 09:22:46 +01:00
0539dd7110
SpinalHDL 1.6.2
2021-12-08 23:45:05 +01:00
6c5908f7a3
Merge pull request #220 from BLangOS/patch-1
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Update DebugPlugin.scala: Add optional readback of hardware breakpoint values
2021-11-15 09:25:00 +01:00
411d946a58
Update DebugPlugin.scala
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Add readback of the hardware breakpoint values.
A new parameter is added to the plugin to switch readback on and off.
2021-11-11 12:12:23 +01:00
acf14385d8
#213 disable pmp test with region overlapping
2021-10-22 17:24:51 +02:00
9df704cad9
Merge pull request #213 from occheung/pmp-fix
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PMP Plugin: Fix PMP region size & priority
2021-10-21 10:13:21 +02:00
a3807660e3
pmp perm: revert to mux for priority
2021-10-19 11:40:39 +08:00
df03c99ab2
pmp_setter: fix mask generation
2021-10-19 11:39:25 +08:00
c3c3a94c5d
IBusSimplePlugin can now use a Vec based buffer
2021-10-13 16:26:16 +02:00
97a3c1955b
VexRiscvSmpCluster add d$ i$ less arg
2021-10-11 11:57:39 +02:00
35754a0709
Fix BrieySim (SpinalSim)
2021-09-25 13:28:37 +02:00
8c0fbcadac
Add BrieySim (SpinalSim)
2021-09-25 13:18:55 +02:00
5f5f4afbf2
Briey revert RVC unwanted addition
2021-09-22 15:01:08 +02:00
b807254759
Briey and Murax verilators now use FST instead of VCD
2021-09-22 12:57:27 +02:00
65cda95176
Fix wishbone bridges with datawidth > 32
2021-09-17 09:43:30 +02:00
c1481ae244
update ScopeProperty usages
2021-09-16 19:08:41 +02:00
42bb1ab591
d$ / i$ toWishbone bridges can now be bigger than 32 bits
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https://github.com/m-labs/VexRiscv-verilog/pull/12
2021-09-15 11:36:51 +02:00
68e704f309
restore avalon d$ tests
2021-09-02 15:42:33 +02:00
efd3cd4737
Merge branch 'master' into dev
2021-09-02 14:16:07 +02:00
cc9f3e753a
Fix d$ toAxi bridge
2021-09-02 14:14:42 +02:00
bc561c30eb
Add PmpPluginOld (support TOR)
2021-09-01 11:27:12 +02:00
5c7e4a0294
#170 wishbone example now set dBusCmdMasterPipe
2021-08-24 23:24:29 +02:00
3deeab42fd
VexRiscvSmpCluster config fix
2021-08-10 12:14:42 +02:00
805bd56077
Fix VexRiscvBmbGenerator.hardwareBreakpointCount default value
2021-07-30 16:51:07 +02:00
671bd30953
Update Bmb invalidate/sync parameters
2021-07-28 13:44:04 +02:00
ba8f5f966a
Vfu typo
2021-07-26 15:27:20 +02:00
b717f228d6
VfuPlugin wip
2021-07-26 15:17:06 +02:00
c242744d02
CfuPlugin now only fork when the rest of the pipeline is hazard free
2021-07-26 14:45:54 +02:00
f3f9b79f9a
VexRiscvSmpCluster earlyShifterInjection added
2021-07-21 18:34:57 +02:00
5fc4125763
Merge branch 'dev'
2021-07-20 11:21:11 +02:00
3028c19389
Fix #191 (data cache toAxi bridge)
2021-07-20 11:20:53 +02:00
Dolu1990
Daniel Schultz
Oscar Shiang
B.Lang
occheung