Charles Papon
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c01c256757
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Revert "Merge branch 'master' into dev"
This reverts commit b5374433a5, reversing
changes made to f01da9c73b.
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2020-01-29 15:20:13 +01:00 |
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Charles Papon
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b5374433a5
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Merge branch 'master' into dev
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2020-01-29 12:50:41 +01:00 |
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Dolu1990
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ac79cc6fe6
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Merge pull request #109 from sebastien-riou/arty
missing tcl files for Murax on Arty
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2020-01-17 12:07:54 +01:00 |
sebastien-riou
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badc38d645
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Merge remote-tracking branch 'origin/master' into arty
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2020-01-17 00:54:19 +01:00 |
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sebastien-riou
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1fb1e358bb
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fix makefile clean target
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2020-01-17 00:49:35 +01:00 |
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sebastien-riou
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2bcddd333d
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forced the commit of missing TCL files
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2020-01-17 00:33:02 +01:00 |
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Dolu1990
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95ec47e5b8
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Merge pull request #108 from sebastien-riou/arty
Murax on Arty A7-35
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2020-01-16 23:21:29 +01:00 |
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sebastien-riou
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97b2838d18
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Murax on Digilent Arty A7-35
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2020-01-16 21:58:55 +01:00 |
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sebastien-riou
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195318b665
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Merge pull request #1 from sebastien-riou/VXIP
Murax_xip: better pin names in scala, bootloader without magic word
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2020-01-13 22:06:31 +01:00 |
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sebastien-riou
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de9f704de2
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better pin names in scala, bootloader without magic word
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2020-01-13 21:58:08 +01:00 |
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Charles Papon
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f01da9c73b
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CsrPlugin add printCsr
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2020-01-13 20:44:55 +01:00 |
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sebastien-riou
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49f502aef4
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Merge branch 'master' of github.com:sebastien-riou/VexRiscv
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2020-01-12 19:52:59 +01:00 |
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sebastien-riou
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bfb0b54f9b
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readme for XIP on Murax improved
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2020-01-12 19:52:27 +01:00 |
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Dolu1990
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b66de1a3c0
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Merge branch 'master' into master
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2020-01-12 17:38:16 +01:00 |
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sebastien-riou
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b866dcb07f
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XIP on Murax improvements
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2020-01-12 16:08:14 +01:00 |
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Dolu1990
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061ebd1b2c
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Fix murax xip bootloader
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2020-01-12 13:27:45 +01:00 |
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Charles Papon
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4c7025b964
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Fix xtval when no exception and read_only
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2020-01-06 20:07:23 +01:00 |
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Charles Papon
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2a06907902
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fix compilation
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2019-12-24 01:09:55 +01:00 |
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Charles Papon
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3b494e97cd
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Moved KeepAttribute to spinal.lib
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2019-12-24 00:43:36 +01:00 |
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Charles Papon
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052c8dd602
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Fix inWfi naming, fix regressions
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2019-12-20 00:21:55 +01:00 |
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Charles Papon
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0702f97806
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CsrPlugin add wfiOutput
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2019-12-19 22:55:17 +01:00 |
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Charles Papon
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e25dfb4fbf
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CsrPlugin now make SATP write rescheduling the next instruction
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2019-12-09 22:23:07 +01:00 |
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Charles Papon
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744b040c70
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Sync CFU progress
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2019-11-29 11:50:00 +01:00 |
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Charles Papon
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7ae218704e
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CsrPlugin now implement a IWake interface
DebugPlugin now wake the CPU if a halt is asked to flush the pipeline
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2019-11-19 18:36:53 +01:00 |
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Dolu1990
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b290b25f7a
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Merge pull request #95 from MarekPikula/patch-1
Update index links in README
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2019-11-09 15:02:56 +01:00 |
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Charles Papon
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6d0d70364c
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Add BranchPlugin.decodeBranchSrc2 for branch target configs
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2019-11-08 14:01:53 +01:00 |
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Charles Papon
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4fe7fa56c7
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GenCustomInterrupt demo now enabled vectored interrupt
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2019-11-07 19:55:26 +01:00 |
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Charles Papon
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bb405e705b
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Add UserInterruptPlugin
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2019-11-07 19:52:45 +01:00 |
Marek Pikuła
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f6e707a639
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Update index links in README
Eclipse links in index were incorrect.
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2019-11-07 14:47:36 +01:00 |
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Charles Papon
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8839f8a8e9
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Fix DBus AXI bridges from writePending counter deadlock
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2019-11-03 16:45:24 +01:00 |
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Charles Papon
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2bf6a536c9
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Fix DBus AXI bridges from writePending counter deadlock
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2019-11-03 16:44:09 +01:00 |
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Charles Papon
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bd2787b562
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RegFilePlugin project X0 against boot glitches if no x0Init but zeroBoot
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2019-11-01 16:24:07 +01:00 |
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Charles Papon
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f2a5134621
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Merge remote-tracking branch 'origin/rpls-mul16'
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2019-10-23 22:29:35 +02:00 |
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Charles Papon
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bb9261773b
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Fix MulDiveIterative plugin when RSx have hazard in the execute stage
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2019-10-23 00:02:08 +02:00 |
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Charles Papon
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67028cdb48
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Add Mul16Plugin to regression tests
Fix missing MulSimplePlugin in regressions tests
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2019-10-21 12:53:53 +02:00 |
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Charles Papon
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8091a872f3
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Fix muldiv plugin for CPU configs without memory/writeback stages
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2019-10-21 12:53:03 +02:00 |
Richard Petri
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2d56c6738c
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Multiplication Plugin using 16-bit DSPs
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2019-10-20 22:24:19 +02:00 |
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Charles Papon
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b4c75d4898
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Merge remote-tracking branch 'origin/dev' into dev
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2019-10-11 00:25:37 +02:00 |
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Charles Papon
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a2b49ae000
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Fix CFU arbitration, add CFU decoder, CFU now redirect custom-0 with func3
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2019-10-11 00:25:22 +02:00 |
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Charles Papon
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310c325eaa
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IBusCached add Keep attribut on the line loader to avoid Artix7 block ram merge, but do not seem to have effect
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2019-10-11 00:24:21 +02:00 |
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Charles Papon
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711eed1e77
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MulPlugin add withInputBuffer feature and now use RSx instead of SRCx
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2019-10-11 00:23:29 +02:00 |
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Charles Papon
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3fc0a74102
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Add Keep attribut on dBusCached relaxedMemoryTranslationRegister feature
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2019-10-11 00:22:44 +02:00 |
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Charles Papon
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51d22d4a8c
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Merge remote-tracking branch 'origin/cfu' into dev
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2019-10-10 15:00:43 +02:00 |
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Charles Papon
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319d162f67
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Merge remote-tracking branch 'origin/tigthlyCoupled' into dev
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2019-10-03 12:33:27 +02:00 |
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Charles Papon
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5df56bea79
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Allow getDrivingReg to properly see i$ decode.input(INSTRUCTION) register
(used to inject instruction from the debug plugin)
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2019-10-03 00:20:33 +02:00 |
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Charles Papon
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ca228a392e
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Merge branch 'short-pipeline-fixes'
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2019-09-26 10:25:11 +02:00 |
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Charles Papon
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8d8c301662
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Merge branch 'short-pipeline-fixes-xobs' into short-pipeline-fixes
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2019-09-23 15:22:27 +02:00 |
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Charles Papon
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49944643d2
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Add regression for data cache without writeback stage, seem to pass tests, including linux ones
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2019-09-23 15:20:51 +02:00 |
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Charles Papon
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bf82829e9e
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Data cache can now be used without writeback stage
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2019-09-23 15:20:20 +02:00 |
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Charles Papon
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ace963b542
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Hazard on memory stage do not need to know if that's bypassable if the memory stage is the last one
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2019-09-21 14:13:28 +02:00 |