Dolu1990
f20eb4d541
Merge pull request #115 from antmicro/fix_emulator
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emulator: Use external hw/common.h from LiteX
2020-04-07 12:29:40 +02:00
Dolu1990
ddc59bc404
Fix DebugPlugin step by step
2020-04-07 12:27:52 +02:00
Dolu1990
5aa0b86d96
Fix DebugPlugin step by step
2020-04-07 12:13:40 +02:00
Dolu1990
a52b833727
fix weird regression testbench memory bug
2020-04-06 21:42:44 +02:00
Dolu1990
a107e45116
fix non smp regression
2020-04-06 06:43:28 +02:00
Dolu1990
ca72a421be
LrSc align software model to the hardware. Linux OK
2020-04-05 21:45:45 +02:00
Dolu1990
2eec18de65
LrSc SMP, linux crash in userspace
2020-04-05 16:28:46 +02:00
Dolu1990
f2ef8e95ab
Implement external LrSc
2020-04-05 11:38:57 +02:00
Dolu1990
ff074459ad
Fix LrSc for configs without mmu
2020-04-04 22:54:35 +02:00
Dolu1990
c9bbf0d12a
update LrSc reservation logic to match the spec
2020-04-04 21:21:35 +02:00
Dolu1990
31d2aaa05b
Update README.md
2020-03-28 15:38:32 +01:00
Dolu1990
2dac7dae32
Fix BranchPlugin.jumpInterface priority to avoid conflicts with other instructions on DYNAMIC_TARGET missprediction
2020-03-28 14:36:06 +01:00
Dolu1990
b3215e8beb
Make things generated in a deterministic order
2020-03-24 13:11:07 +01:00
Dolu1990
31667b18d8
Update README.md
2020-03-20 11:26:38 +01:00
Dolu1990
97258c214a
Merge pull request #115 from antmicro/fix_emulator
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emulator: Use external hw/common.h from LiteX
2020-03-18 12:02:27 +01:00
Dolu1990
c122365a52
Smp spec update, add Interface subsets (writeOnly, readOnly)
2020-03-11 14:20:13 +01:00
Dolu1990
95237b23ea
SpinalHDL 1.4.0
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Merge branch 'dev'
2020-03-09 13:49:06 +01:00
Dolu1990
ab2f4cd2b7
Merge branch 'master' into dev
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# Conflicts:
# README.md
# build.sbt
2020-03-09 13:41:23 +01:00
Dolu1990
5f90702b2f
SpinalHDL update
2020-03-09 13:14:16 +01:00
Dolu1990
defe3c5558
DataCache relax flush timings
2020-03-08 12:35:24 +01:00
Dolu1990
04bf1a4ced
Fix build.sbt
2020-03-08 00:23:19 +01:00
Dolu1990
7a5afb86a5
Fix build.sbt
2020-03-07 19:09:33 +01:00
Dolu1990
97db4f02a0
Merge branch 'rework_fetch' into dev
2020-03-07 18:22:46 +01:00
Dolu1990
44005ebf31
update Synthesis results
2020-03-07 18:22:01 +01:00
Charles Papon
2c6076ba97
improve smp spec
2020-03-07 13:35:21 +01:00
Charles Papon
b7ae902bbc
smp spec improvements, no more read abort
2020-03-05 00:14:11 +01:00
Charles Papon
58af94269e
add CsrPlugin.csrOhDecoder
2020-03-05 00:13:04 +01:00
Charles Papon
50ec0a1917
update readme perf
2020-03-05 00:12:46 +01:00
Charles Papon
505d0b700a
MulDivPlugin now give names to div stages
2020-03-04 19:58:54 +01:00
Dolu1990
0a212c91fd
update synthesisBench paths
2020-03-04 18:13:56 +01:00
Dolu1990
ff5cfc0dde
Fix DebugPlugin step
2020-03-03 18:27:53 +01:00
Dolu1990
12463e40a4
improve debugPlugin step logic
2020-03-03 15:59:30 +01:00
Charles Papon
fd37962a58
typo
2020-03-03 10:56:12 +01:00
Dolu1990
ef5398ce21
Fix #117 DataCache mem blackboxing
2020-03-02 14:24:27 +01:00
Dolu1990
54581f6d9e
Fix #117 DataCache mem blackboxing
2020-03-02 14:23:59 +01:00
Dolu1990
78d4660282
Merge branch 'dev' into rework_fetch
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# Conflicts:
# src/test/scala/vexriscv/TestIndividualFeatures.scala
2020-03-01 22:58:25 +01:00
Dolu1990
ea5464ea26
TestIndividualFeatures is now multithreaded
2020-03-01 21:40:53 +01:00
Dolu1990
02545b9bea
typo
2020-03-01 13:03:40 +01:00
Dolu1990
559260020b
Improve testing infrastructure with more options and better readme
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https://github.com/litex-hub/linux-on-litex-vexriscv/issues/112
2020-03-01 13:02:08 +01:00
Dolu1990
0c7556ad7f
Update README.md
2020-02-29 23:46:21 +01:00
Charles Papon
25d880f6c7
Fix synthesis bench
2020-02-28 18:20:08 +01:00
Charles Papon
c94d8f1c6c
Fetcher and IBusSimplePlugin flush reworked
2020-02-28 17:23:44 +01:00
Charles Papon
492310e6fa
DBusCachedPlugin fix noWriteBack redo priority
2020-02-28 17:21:59 +01:00
Charles Papon
76d063f20a
Fix MulPlugin keep attribute
2020-02-24 22:43:08 +01:00
Mateusz Holenko
f88b259eba
emulator: Use external hw/common.h from LiteX
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Remove code copied from `hw/common.h` and use
the header from the LiteX repository provided
using `LITEX_BASE` environment variable.
Content of `common.h` is now evolving (new functions
are added, some are removed) and syncing it
between repos would be cumbersome.
2020-02-24 14:27:45 +01:00
Charles Papon
999a868c14
Update readme VexRiscv perf numbers
2020-02-24 00:07:14 +01:00
Charles Papon
485b4a5838
Improve maxPerf configs
2020-02-23 23:52:43 +01:00
Charles Papon
fad09e805f
Add Fetcher.predictionBuffer option to pipeline BRANCH_TARGET, higher FMax, about 1 ns critical path gain on Arty7 => 5 ns
2020-02-23 23:18:27 +01:00
Charles Papon
67d2071a32
typo
2020-02-23 23:17:02 +01:00
Charles Papon
c8016e90a4
MulPlugin now add KEEP attribute on RS1 and RS2 to force Vivado to not retime it with the DSP
2020-02-23 20:25:31 +01:00