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558 Commits 5 Branches 14 Tags 5.7 MiB
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558 Commits

Author SHA1 Message Date
Florent Kermarrec ae6f10a7e1 sdram_init: use 60ohm as rtt_wr default value 
Seems the best for point to point according to tn4113_ddr3_point_to_point_design
 2018-08-21 15:58:07 +02:00
enjoy-digital cd330b4b44
Merge pull request #28 from AlphamaxMedia/refactor-master 
i think there's a missing "self" in the params
 2018-08-21 15:22:50 +02:00
Florent Kermarrec 522cbc97a1 frontend: add AXI support for dma and bist 2018-08-21 14:49:10 +02:00
Florent Kermarrec 57157345cf frontend: add initial AXI support 2018-08-21 13:39:46 +02:00
Florent Kermarrec 97349bc11b frontend: rename bridge to wishbone and LiteDRAMWishboneBridge to LiteDRAMWishbone2Native 2018-08-21 13:27:49 +02:00
Florent Kermarrec 2b20c11e2d add LiteDRAMNativePort to prepare for AXI, change some internals and API of get_port but keep retro-compatibility 
- LiteDRAMPort -> LiteDRAMNativePort
- aw -> address_width
- dw -> data_width
- cd -> clock_domain
 2018-08-21 13:21:04 +02:00
bunnie 818c6785f0 update module settings to reflect latest changes 2018-08-21 17:59:54 +08:00
bunnie c9b8db5dc9 i think there's a missing "self" in the params 2018-08-21 17:28:42 +08:00
Florent Kermarrec 0b6e21ab6d improve ddr3 electrical settings 2018-08-21 10:45:42 +02:00
bunnie 697eaafc4c add board tuning parameters 2018-08-21 09:20:21 +02:00
Florent Kermarrec 9a57c4e88c phy/s7ddrphy: add DDR3-800 timings 2018-08-21 09:02:57 +02:00
Florent Kermarrec 9401b92c71 move sdram_init to litedram 2018-08-20 15:37:39 +02:00
Florent Kermarrec 209dc0d781 frontend/bist: add dynamic random data and addressing 2018-08-17 13:49:27 +02:00
Florent Kermarrec b13962c7bd core/multiplexer: fix 1:1 2018-08-16 15:48:26 +02:00
Florent Kermarrec a215ac7d8b core/multiplexer: fix count signal width (when max<2) 2018-08-16 15:33:03 +02:00
Florent Kermarrec ad8438f5d3 core/controller: enable auto_precharge by default 2018-08-15 17:04:16 +02:00
Florent Kermarrec bba491396f core/bankmachine: fix auto_precharge (OR on the two buffers for req.lock), don't need to wait for precharge timer to issue auto-precharge 2018-08-15 17:03:06 +02:00
Florent Kermarrec 2e362ee160 core/bankmachine: add auto_precharge setting to enable/disable auto_precharge mode (disabled by defaut) 2018-08-15 16:13:39 +02:00
Florent Kermarrec 6d234219b4 core/bankmachine: rename cmd_bufferPre to cmd_buffer_lookahead 2018-08-15 13:30:06 +02:00
Florent Kermarrec 23358b5d29 core/multiplexer: use self.submodules for timing controllers, fix tFAW count 2018-08-15 13:04:19 +02:00
enjoy-digital db4ec67741
Merge pull request #24 from JohnSully/AutoPrecharge 
Auto precharge
 2018-08-15 12:46:29 +02:00
627cccde59 Fix tCCD timing which watched the wrong command 2018-08-14 23:55:01 -04:00
16a852bda5 Revert "core/refresher: synchronize valid" 
This reverts commit 6620a91a22 because it fails to issue a refresh command
 2018-08-14 23:23:24 -04:00
a4be642d56 Fix multiple timings ignored 2018-08-14 22:42:02 -04:00
771ccfdc41 Merge branch 'master' of https://github.com/enjoy-digital/litedram into AutoPrecharge 2018-08-14 15:25:21 -04:00
Florent Kermarrec 6620a91a22 core/refresher: synchronize valid 2018-08-14 15:30:24 +02:00
Florent Kermarrec b2f1f29384 core/bankmachine: update comments 2018-08-14 15:13:33 +02:00
Florent Kermarrec c1b1b07b3c core/multiplexer: synchronize ready on tXXDController and tFAWcontroller to improve timings 2018-08-14 15:13:10 +02:00
Florent Kermarrec 147466beec multiplexer: create timing controllers module and simplify 2018-08-14 11:05:09 +02:00
enjoy-digital eeb57ad43d
Merge pull request #23 from JohnSully/outoforder 
Out of Order Completion
 2018-08-11 08:58:28 +02:00
32069858ee When auto-precharging assert track_close 2018-08-10 20:48:30 -04:00
74279ea26a Enable auto-precharge 2018-08-10 19:19:02 -04:00
03a2ad6bdc Ensure out of order is on a per-bank basis 2018-08-10 16:35:16 -04:00
86b3e2d2ef Add reorder flag to the crossbar 2018-08-10 15:54:22 -04:00
77c513d0f0 Merge upstream. UNTESTED 2018-08-10 00:31:00 -04:00
8266a6e690 Prevent compilation failures when tRRD == 0 2018-08-10 00:21:22 -04:00
ed4be0b2a0 Add write bank to out of order interface 2018-08-10 00:20:13 -04:00
Florent Kermarrec c28a754867 test: update 2018-08-09 10:54:42 +02:00
Florent Kermarrec f7f8452857 core: make rdata_bank optional (break cdc when enabled), fix some usecases 2018-08-09 10:54:30 +02:00
Florent Kermarrec 873b970fca frontend: avoid breaking api with last rbank change (use bankbits_max), some cleanup 2018-08-09 09:33:24 +02:00
enjoy-digital 26f3f016e1
Merge pull request #21 from JohnSully/outoforder 
Outoforder
 2018-08-09 09:20:55 +02:00
enjoy-digital 74c3c092ea
Merge pull request #20 from bunnie/400mhz-pr 
add 400MHz tap setting (valid for -3 and -2/2E speed grades)
 2018-08-09 08:20:29 +02:00
Tim Ansell 48230583b9
Adding comment to iodelay_tap_average dictionary. 2018-08-08 13:31:11 -07:00
bunnie d986b60e03 add 400MHz tap setting (valid for -3 and -2/2E speed grades) 2018-08-09 03:28:48 +08:00
Florent Kermarrec e02a251cde core: make tRRD definition optional and some cosmetic changes 2018-08-08 12:24:07 +02:00
bfa1d6aa7e remove debug prints 2018-08-03 15:24:08 -04:00
2fa2a6d9f2 Initial implementation of out of order controller 2018-08-03 15:21:17 -04:00
enjoy-digital 5d74eb249f
Merge pull request #19 from JohnSully/timing 
Fix timing issues (tRRD, tCCD, and tFAW)
 2018-07-31 21:37:28 +02:00
f1fea6dbd6 Correct tWTR timing: 1) timing starts after the completion of the write burst, 2) We don't need to wait on switches if a write hasn't taken place recently 2018-07-31 13:31:49 -04:00
eb3f4a05f6 fix CAS to CAS timings (needs to account for multiple banks) 2018-07-31 01:57:55 -04:00