062177502b
phy: add bitslip module (we need to implement it in logic for Kintex Ultrascale since not provided by ISERDESE3)
2017-02-10 08:59:13 +01:00
1430cb3d49
phy: add initial Kintex Ultrascale PHY (incomplete)
...
Input deserializer still missing, need to implement bitslip in logic and use new fifo interface.
Others primitives should be fine.
2017-02-09 13:25:45 +01:00
99550968e7
test: move BISTDriver to common and use it in test_bist_async
2017-01-17 15:18:10 +01:00
1bcab6303d
setup.py: add test_suite
2017-01-17 15:17:21 +01:00
d213a628f8
test/test_bist: use generator to corrupt memory (allow testing base address on checker/generator)
2017-01-17 14:35:34 +01:00
40168db0b4
test/test_bist: create BISTDriver to simplify test code
2017-01-17 14:31:24 +01:00
4f51524921
frontend/bist: rename err_count to errors
2017-01-17 14:30:23 +01:00
c56f90e865
test/test_bist: simplify and test modules directly not through CSR
2017-01-17 14:14:50 +01:00
e7fe539c73
frontend/bist: remove LiteDRAMBISTCheckerScope.
...
Checker should not be used to investigate errors but only to verify that is already validated still works. (ie we don't want to be able to understand what is going on, just to know if it's working or not). To understand what is going on we will look at signals with LiteScope and eventually trigger on err_count from checker.
2017-01-17 13:48:03 +01:00
ad304c8997
test: convert to python unittests and some cleanup
2017-01-17 13:18:11 +01:00
53d11cf7e3
Merge pull request #5 from mithro/scope
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Creating a utility module for easily scoping the LiteDRAMBISTChecker module.
2016-12-24 15:16:36 +01:00
c142db3966
Creating a utility module for easily scoping the LiteDRAMBISTChecker module.
2016-12-19 17:49:24 +01:00
aac61f346e
test: start fixing bist_tb
2016-12-17 19:24:12 +01:00
0f151c5499
frontend/bist: small cleanup
2016-12-17 19:22:56 +01:00
a613c49783
frontend/bist: cleanup the way we expose signals for debugging
2016-12-17 19:04:58 +01:00
c090593e52
Merge pull request #3 from mithro/bist
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Improve the BIST testbench and documentation
2016-12-17 18:33:38 +01:00
e21b45b608
Merge remote-tracking branch 'upstream/master' into bist
2016-12-17 18:15:59 +01:00
bc75d4f3d5
bist: Reworking as suggested by Florent.
2016-12-17 17:49:47 +01:00
5909e5d76e
frontend/bist: refactor(simplify) LiteDRAMBISTChecker
2016-12-17 17:08:50 +01:00
381789c84d
frontend/bist: refactor(simplify) LiteDRAMBISTGenerator, use start instead of shoot
2016-12-17 16:38:59 +01:00
70a333628b
dma: Adding some documentation.
2016-12-17 14:09:50 +01:00
fcc1d5059e
bist: Improving documentation a bit.
2016-12-17 14:09:50 +01:00
f1ad8991a4
bist: Working on improving the names of things.
2016-12-17 14:09:50 +01:00
8ff2f8779b
bist: Adding "halt on error" functionality.
...
Also include ability to see address of error and expected verse actual
data values.
Extend the test bench to test this functionality.
2016-12-17 14:09:50 +01:00
c0b8d1a714
bist: Adding some documentation.
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(Plus small formatting cleanup.)
2016-12-17 14:09:50 +01:00
da144f41d4
bist: Refactoring test bench.
...
Move a bunch of common code into common.py
2016-12-17 14:09:50 +01:00
dc14a98bf4
bist: s/shoot/start/
2016-12-17 14:09:50 +01:00
086b905e59
bist: Improve the basic test bench a little.
2016-12-17 14:09:50 +01:00
6ae11fa5c8
bist: Make reset write to activate like shoot.
2016-12-17 14:09:50 +01:00
85e4b65550
bist: Small formatting change.
2016-12-17 14:09:50 +01:00
e901305e56
bist: Done only goes high after bist runs.
2016-12-17 14:09:50 +01:00
f57dfad6a4
frontend: add flush signal on dram ports and fix a specific case in LiteDRAMReadPortUpConverter
2016-12-15 19:07:43 +01:00
bd40268961
frontend/dma: add fifo_buffered parameter
2016-10-28 09:48:25 +02:00
6e3f5e4d98
frontend: add reverse parameter to converters
2016-06-21 17:29:12 +02:00
2ed7212701
frontend/crossbar: fix sign on adr_shift
2016-06-20 21:40:32 +02:00
ad8ca86e13
frontend/adaptation: implement LiteDRAMReadPortUpConverter correctly
...
still some corner cases to manage
2016-06-15 23:57:16 +02:00
5823373243
frontend: introduce mode on ports: write, read or both
2016-06-15 17:51:46 +02:00
b0382e8776
frontend/crossbar: add clock domain crossing and data width convertion to get_port
2016-06-13 14:41:57 +02:00
ed997f1cfe
core: fix refresh (bug was reducing controller throughput by 2)
2016-06-13 13:11:41 +02:00
870638fc50
frontend/adaptation: small optimization on LiteDRAMPortUpConverter (still to be refactored)
2016-06-12 16:53:44 +02:00
edbebfa8a2
frontend/adaptation: add workaround on LiteDRAMPortUpConverter to increase throughput on reads (to be fixed since only working for our actual usecase)
2016-06-10 22:07:53 +02:00
66907f1468
frontend/adaptation: expose LiteDRAMPortDownConverter, LiteDRAMPortUpConverter
2016-06-10 19:13:12 +02:00
e2b6bda7d0
test: add random and autocheck on downconverter_tb and upconverter_tb
2016-06-08 17:33:21 +02:00
afd2e441eb
frontend/adaptation: fix some comments
2016-06-08 17:32:08 +02:00
25c5a8aaf5
frontend/adaptation: adapt fifo depths
2016-06-02 22:35:27 +02:00
0faee6639d
frontend/bist: add random parameter on generator/checker to ease debug
2016-06-02 18:35:45 +02:00
a5ff573046
frontend/bist: rename generator/checker to core
2016-06-02 09:27:46 +02:00
41364dd0b1
frontend/bist: fix cd on LiteDRAMBISTChecker, bist_async_tb now working
2016-05-29 16:00:35 +02:00
cb69561137
phy/model: add we_granularity parameter as simulator bug workaround (to be removed)
2016-05-28 13:02:40 +02:00
8ee2992e5b
frontend/bist: simplify and use incrementing addressing
2016-05-26 12:04:41 +02:00
Florent Kermarrec
Tim 'mithro' Ansell