Florent Kermarrec
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6fa891d5d6
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frontend/axi: fix write response for bursts
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2018-11-12 18:02:54 +01:00 |
|
Florent Kermarrec
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93e8510f55
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test/test_axi: add bursts to axi2native
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2018-11-12 18:00:28 +01:00 |
|
Florent Kermarrec
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e27fbc2430
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test/test_axi: move definitions to top and make Access herit from Burst
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2018-11-12 13:09:05 +01:00 |
|
Florent Kermarrec
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4470f32ef8
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test/test_axi: change order of the tests
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2018-11-12 12:59:19 +01:00 |
|
Florent Kermarrec
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070cc26994
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test/test_axi: use separate generator for writes cmd/data
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2018-11-12 12:58:19 +01:00 |
|
Florent Kermarrec
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127e9285a3
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frontend/wishbone: simplify LiteDRAMWishbone2Native code (resource usage almost the same)
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2018-11-09 15:44:49 +01:00 |
|
Florent Kermarrec
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ca82ac18d0
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frontend/wishbone: add LiteDRAMWishbone2AXI
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2018-11-09 15:32:49 +01:00 |
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Florent Kermarrec
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3586e157f2
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frontend/axi: improve len/size comment (-1), set default id_width to 1
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2018-11-09 15:29:31 +01:00 |
|
Florent Kermarrec
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71be616817
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frontend/axi: be sure wdata is available before sending the command to the controller
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2018-11-09 11:33:01 +01:00 |
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Florent Kermarrec
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55b5f40e00
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modules: add AS4C256M16D3A
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2018-11-08 16:40:38 +01:00 |
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enjoy-digital
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69ea8668d0
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Merge pull request #62 from daveshah1/AS4C32M16
modules: Add AS4C32M16 32Mx16 SDRAM
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2018-11-06 14:50:14 +01:00 |
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Florent Kermarrec
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b41fe61b2a
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phy/kusddrphy/ddr4: multiplexed address bits are always the same (14, 15, 16) and fix ba/bg ordering
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2018-11-05 17:00:47 +01:00 |
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Florent Kermarrec
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2e1978728c
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phy/kusddrphy: add dfi mux on address/control signals
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2018-11-05 15:41:22 +01:00 |
David Shah
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3a5d45bd5e
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modules: Add AS4C32M16 32Mx16 SDRAM
Signed-off-by: David Shah <dave@ds0.me>
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2018-11-05 12:26:20 +00:00 |
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Florent Kermarrec
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a8c3d394ec
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sdram_init: fix compilation
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2018-11-05 10:46:47 +01:00 |
|
Florent Kermarrec
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af344897eb
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common: add DDR4 burst_length
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2018-11-05 10:46:34 +01:00 |
|
Florent Kermarrec
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2a9fb11b02
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phy/kusddrphy: more genericity, initial DDR4 support
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2018-11-05 10:46:18 +01:00 |
|
Florent Kermarrec
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ae5dc9f27a
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sdram_init: add initial DDR4 initialization
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2018-11-05 09:32:08 +01:00 |
|
Florent Kermarrec
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8181fea0da
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modules: add EDY4016A DDR4
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2018-11-04 18:50:50 +01:00 |
|
Florent Kermarrec
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346e64c3f2
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frontend/ecc: fix typo
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2018-11-04 17:07:00 +01:00 |
|
Florent Kermarrec
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82c08c78c9
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phy/gensdrphy: use tristate input
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2018-10-29 19:27:26 +01:00 |
|
Florent Kermarrec
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9ce84d96ec
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modules: add MT48LC16M16 (ulx3s)
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2018-10-29 19:26:42 +01:00 |
|
Florent Kermarrec
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f36bcff49f
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phy/gensdrphy: cleanup/simplify pass
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2018-10-19 18:26:45 +02:00 |
|
Florent Kermarrec
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da06715596
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core/bankmachine: typo
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2018-10-19 18:20:12 +02:00 |
|
Florent Kermarrec
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ab0d519ebb
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core: change cba_shift parameter to more explicit address_mapping parameter
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2018-10-19 17:38:04 +02:00 |
|
Florent Kermarrec
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230ea24113
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core: simplify/cleanup pass
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2018-10-19 17:21:06 +02:00 |
|
Florent Kermarrec
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94b844d5b0
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core/frontend: move crossbar to core
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2018-10-19 15:07:39 +02:00 |
|
Florent Kermarrec
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8d24163a86
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phy/s7ddrphy: use our own bitslip module in fabric
we could probably reduce added latency to 2 or 1 in the future.
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2018-10-18 13:40:58 +02:00 |
|
Florent Kermarrec
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20d767532d
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phy/s7ddrphy: add additional_read_latency parameter
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2018-10-15 11:10:16 +02:00 |
|
Florent Kermarrec
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f11506accd
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examples/litedram_gen: cleanup pins definition
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2018-10-15 09:38:34 +02:00 |
|
Florent Kermarrec
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75b314c8eb
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modules: update K4B2G1646F and use timings from datasheet
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2018-10-15 08:51:08 +02:00 |
|
Florent Kermarrec
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b71ed354ad
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core/bankmachine: manage tRC
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2018-10-15 08:34:41 +02:00 |
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Florent Kermarrec
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0abb3e4f5d
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modules: use tRAS and tRP to compute tRC (tRC = tRAS + tRP)
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2018-10-15 08:34:18 +02:00 |
|
Florent Kermarrec
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9a950f051a
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ecc: update core/test
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2018-10-12 17:13:53 +02:00 |
|
Florent Kermarrec
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8a0d0f09f9
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phy/s7ddrphy: remove hacky bl8 variant (see #60)
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2018-10-12 08:59:33 +02:00 |
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Florent Kermarrec
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5fe4868491
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modules: add trrd to all ddr3 modules
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2018-10-12 08:19:38 +02:00 |
|
enjoy-digital
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dbfa929bec
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Merge pull request #59 from enjoy-digital/tRRD_Fix
tRRD incorrectly specified
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2018-10-12 07:21:22 +02:00 |
john@csquare.ca
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5315d279d3
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tRRD incorrectly specified
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2018-10-11 17:08:31 -04:00 |
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Florent Kermarrec
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167c0c91f6
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remove partial reordering code in master, keep things in bank_reordering branch.
we'll try to stabilize master without reordering, then do some refactoring/adding a test suite to ease adding proper reordering later
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2018-10-11 19:40:31 +02:00 |
|
Florent Kermarrec
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828129ef40
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core/bank_machine: simplify trascon
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2018-10-10 17:48:11 +02:00 |
|
Florent Kermarrec
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4fa64c8e96
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core/bankmachine: remove trccon (activate_allowed not used)
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2018-10-10 17:44:40 +02:00 |
|
John Sully
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feac98f399
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core/bankmachine: use tXXDController everywhere (better timings)
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2018-10-10 17:42:57 +02:00 |
|
John Sully
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bce411ec95
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common: move tXXDController to common
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2018-10-10 17:28:32 +02:00 |
|
Florent Kermarrec
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fef4701a45
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core/multiplexer: select all ranks on refresh
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2018-10-10 09:13:20 +02:00 |
|
Florent Kermarrec
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3481d45c9b
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core/multiplexer: fix rank_decoder width
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2018-10-09 14:24:39 +02:00 |
|
Florent Kermarrec
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3b5a1ff906
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modules: add K4B1G0446F
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2018-10-08 17:36:32 +02:00 |
|
Florent Kermarrec
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48c17ce8a4
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modules: fix tWTR regression on MT46H32M32
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2018-10-02 18:53:13 +02:00 |
|
Florent Kermarrec
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ad0a1d4215
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modules: improve timings definition (keep retro-compatibility with previous definitions)
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2018-10-02 10:32:45 +02:00 |
|
Florent Kermarrec
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5b02791580
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modules: add tCCD to all modules
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2018-10-02 08:41:48 +02:00 |
Tim 'mithro' Ansell
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6c7a804986
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Adding tCCD for DDR2 modules.
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2018-10-01 19:01:12 -07:00 |