94241d0583
bench: use new platform.request_all on LedChaser.
2020-08-06 20:03:03 +02:00
74205979bd
bench: add genesys2 bench.
2020-08-06 19:19:45 +02:00
37fb44f33e
add bench directory with a first bench on arty board.
...
The aim is to create an automated hardware bench, control is done over Etherbone
(but could also be done over UARTBone, PCIe, USB, etc...) and various frequencies
are tested and BIOS logged.
It would also be useful to be able to recompile/reload BIOS in this bench to easily
test software changes and verify it works with various frequencies.
Can be tested with:
./arty.py --build --load
lxserver --udp
./arty.py --test
Dump Main PLL...
ClkReg1:
low_time: 8
high_time: 8
reserved: 1
phase_mux: 0
Reconfig Main PLL to 133.33333333333331MHz...
Measuring sys_clk...
sys_clk: 133.72MHz
Reset SoC and get BIOS log...
__
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2020 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Aug 6 2020 18:49:15
BIOS CRC passed (44c8f057)
Migen git sha1: 7bc4eb1
LiteX git sha1: 188e6f57
--=============== SoC ==================--
CPU: VexRiscv @ 100MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 32KiB
SRAM: 8KiB
L2: 8KiB
MAIN-RAM: 262144KiB
--========== Initialization ============--
Initializing DRAM @0x40000000...
SDRAM now under software control
SDRAM now under software control
Read leveling:
m0, b00: |00000000000000000000000000000000| delays: -
m0, b01: |00000000000000000000000000000000| delays: -
m0, b02: |00000000000000000000000000000000| delays: -
m0, b03: |00000000000000000000000000000000| delays: -
m0, b04: |00000000000000000000000000000000| delays: -
m0, b05: |00000000000000000000000000000000| delays: -
m0, b06: |00000000000000000000000000000000| delays: -
m0, b07: |00000000000000000000000000000000| delays: -
m0, b08: |00000000000000000000000000000000| delays: -
m0, b09: |11111111111000000000000000000000| delays: 05+-05
m0, b10: |00000000000111111111110000000000| delays: 16+-05
m0, b11: |00000000000000000000000111111111| delays: 27+-04
m0, b12: |00000000000000000000000000000000| delays: -
m0, b13: |00000000000000000000000000000000| delays: -
m0, b14: |00000000000000000000000000000000| delays: -
m0, b15: |00000000000000000000000000000000| delays: -
best: m0, b09 delays: 05+-05
m1, b00: |00000000000000000000000000000000| delays: -
m1, b01: |00000000000000000000000000000000| delays: -
m1, b02: |00000000000000000000000000000000| delays: -
m1, b03: |00000000000000000000000000000000| delays: -
m1, b04: |00000000000000000000000000000000| delays: -
m1, b05: |00000000000000000000000000000000| delays: -
m1, b06: |00000000000000000000000000000000| delays: -
m1, b07: |00000000000000000000000000000000| delays: -
m1, b08: |00000000000000000000000000000000| delays: -
m1, b09: |11111111111000000000000000000000| delays: 05+-05
m1, b10: |00000000000011111111111000000000| delays: 17+-05
m1, b11: |00000000000000000000000011111111| delays: 28+-04
m1, b12: |00000000000000000000000000000000| delays: -
m1, b13: |00000000000000000000000000000000| delays: -
m1, b14: |00000000000000000000000000000000| delays: -
m1, b15: |00000000000000000000000000000000| delays: -
best: m1, b09 delays: 05+-05
SDRAM now under hardware control
Memtest at 0x40000000...
[########################################]
[########################################]
Memtest OK
Memspeed at 0x40000000...
Writes: 212 Mbps
Reads: 188 Mbps
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex> Reconfig Main PLL to 114.28571428571428MHz...
2020-08-06 19:05:20 +02:00
4e62d28af6
examples/.yml: set cmd_latency to 1 on Kintex7/Ultrascale (values valided in LiteX-Boards).
2020-08-06 11:52:34 +02:00
07bf34d0e7
frontend/wishbone: revert non-FSM version, the FSM one does not seem to cover all cases.
2020-08-05 15:48:23 +02:00
9c5ce52b88
common: add connect method to LiteDRAMNativePort and use it in adapter for identify converter.
2020-08-05 12:17:25 +02:00
06f7192fb6
frontend/adapter/LiteDRAMNativePortConverter: simplify using ratio.
2020-08-05 11:41:54 +02:00
a3dfc1db25
frontend/adapter: minor cleanups.
2020-08-05 11:34:49 +02:00
deac4c8134
frontend/adapter: simplify LiteDRAMNativePortDownConverter.
2020-08-05 11:28:44 +02:00
ce4e7f9ad0
frontend/adapter: simplify LiteDRAMNativePortCDC using stream.ClockDomainCrossing.
2020-08-05 11:24:48 +02:00
16fd46bf35
frontend: rename adaptation to adapter.
2020-08-05 11:10:42 +02:00
4970c8aa8c
frontend/wishbone: simplify/review and get FSM back (ease comprehension).
2020-08-05 11:05:00 +02:00
47a0d5fb9e
litedram_gen/LiteDRAMUSDDRPHYCRG: remove AsyncResetSynchronizer on sys/sys4x (reset handled by USIDELAYCTRL).
2020-07-29 08:12:49 +02:00
02e67ec7c5
Merge pull request #192 from antmicro/jboc/port-adaptation
...
Implement LiteDRAMNativePortUpConverter with mode="both"
2020-07-28 19:02:33 +02:00
71b991ec08
Merge pull request #210 from oskirby/ddr3-tdqs-mode
...
Add support for TDQS mode.
2020-07-27 10:52:48 +02:00
805a37447c
Add support for TDQS mode.
...
This adds an optional argument to add_electrical_settings() that can
enable the TDQS mode for x8 DDR3 modules. Normally this would be used
when mixing x4 and x8 modules (eg: heterogenous DIMMS), but it can
also workaround boards with missing or broken DM signals.
2020-07-26 15:51:07 -07:00
c01e86865f
phy/gensdrphy/HalfRateGENSDRPHY: review/simplify and reduce read_latency by 1.
2020-07-24 11:07:15 +02:00
f51052f8b7
core/controller: fix burst_length regression introduced by #206 .
2020-07-18 23:06:11 +02:00
c4ac887ec2
Merge pull request #206 from antmicro/jboc/gensdrphy
...
Add HalfRate GENSDRPHY
2020-07-15 08:19:37 +02:00
2c5fc6621a
phy/gensdrphy: fix problems with half-rate phy, tested on minispartan6
2020-07-14 10:58:58 +02:00
7f55e2e2c5
phy/gensdrphy: add half-rate PHY
2020-07-13 17:03:01 +02:00
edd5e0ec78
phy/gensdrphy: padd clk to SDROutput/SDRInput/SDRTristate.
2020-07-08 07:00:11 +02:00
a8fa38e286
phy/ecp5ddrphy: cosmetic cleanups.
2020-06-30 09:25:44 +02:00
8c339b9945
litedram_gen: update ECP5 clocking.
2020-06-29 19:30:13 +02:00
f6cc1cdb08
litedram_gen: increase integrated_rom_size to 0x8000.
2020-06-29 19:28:11 +02:00
9044c10408
phy/ecp5ddrphy: use sys_rst instead of sys2x_rst as reset on primitives and do sys2x reset externally.
2020-06-29 16:09:14 +02:00
fa7d91a053
phy/ecp5: simplify/fix dqs_oe/dq_oe and revert BitSlip on dq_i_data.
...
dq/dqs_oe was one cycle of and BitSlip on dq_i_data is required for correct initialization.
2020-06-29 16:06:56 +02:00
8c112c709c
Merge pull request #207 from ozbenh/sim-autoinit
...
dfii: Really default to HW control
2020-06-10 10:36:05 +02:00
4580882c69
dfii: Really default to HW control
...
Looks like there was a typo in commit
a595fe07f2
2020-06-10 16:06:46 +10:00
52d7dbe3a6
frontend/fifo: make sure FIFO is only used on LiteDRAMNativePort, expose writer/reader fifo depth, add separators and update copyrights.
2020-06-04 09:26:13 +02:00
c4c8803f4f
Merge pull request #204 from antmicro/jboc/spd-read
...
Add DDR4 SPD EEPROM data parser
2020-06-04 08:54:59 +02:00
067e8a5eb3
Merge pull request #205 from antmicro/jboc/fifo
...
frontend/fifo: increase FIFO level only after data has actually been written
2020-06-04 08:41:04 +02:00
e5179eb9ab
gen: fix LiteDRAMFIFO parameters
2020-06-03 17:39:45 +02:00
8fedc3fcd2
frontend/fifo: increase FIFO level after data has actually been written
2020-06-03 16:13:28 +02:00
992f80c68b
litedram_gen: add Ultrascale(+) support and KCU105 config file, remove cmd_delay on 7-series (not automatically calibrated).
2020-06-03 09:35:40 +02:00
361d250677
litedram_gen: avoid second S7PLL for iodelay clk, generate it from main S7PLL on CLKOUT0 (with fractional divide).
2020-06-03 09:04:00 +02:00
1b56dcf364
litedram_gen: add more memtype asserts, remove csr_alignment (now fixed to 32-bit).
2020-06-03 08:57:31 +02:00
a595fe07f2
dfii: simplify control using CSRFields.
2020-06-02 16:31:33 +02:00
899462c864
Merge pull request #202 from ozbenh/sim-autoinit
...
Default to HW control for sim
2020-06-02 15:48:41 +02:00
863c45a114
test/spd_data: add missing files to tracking
2020-06-02 15:19:53 +02:00
cbd90877b0
modules/spd: select tFAW_min_ck depending on page size
2020-06-02 12:19:38 +02:00
a8f2c044c9
modules: add DDR4SPDData parser
2020-06-02 12:16:41 +02:00
d62fd24c81
Merge pull request #201 from antmicro/jboc/spd-read
...
modules/spd: save SPD data in SDRAMModule
2020-06-01 21:16:58 +02:00
4233f86112
modules/spd: save SPD data in SDRAMModule to allow for runtime verification
2020-06-01 16:56:41 +02:00
f3f89ed8d1
Default to HW control for sim
...
(needs corresponding sdram.c fix in litex)
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-06-01 23:44:59 +10:00
f23cb8056d
litedram_gen: revert builder.build(..., regular_comb=False).
2020-05-27 19:56:00 +02:00
d1db115d6c
litedram_gen: review/simplify #197 .
2020-05-27 19:42:40 +02:00
a8e281f7c5
Merge pull request #197 from ozbenh/standalone-sim
...
Allow generation of a standalone sim model
2020-05-27 19:16:00 +02:00
83b9a1d798
Merge pull request #199 from antmicro/jboc/spd-read
...
modules: add function for parsing SPD EEPROM dumps from BIOS firmware
2020-05-27 14:57:16 +02:00
d0f0c94652
phy/model: Don't generate empty mem_*.init files
...
When using the SDRAM PHY model without specified init data, the
generator still generates a bunch of $readmemh for each bank
reading mem.init, mem_1.init etc... all of which are 0-sized files.
This is cumbersome especially when using a standalone model in
an external project.
This is fixed by having the default bank_init be set to a list
of "None" rather than a list of empty lists.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-22 18:09:11 +10:00
Florent Kermarrec
Owen Kirby
Jędrzej Boczar
Benjamin Herrenschmidt