Commit Graph

147 Commits

Author SHA1 Message Date
Florent Kermarrec 7ea734381e phy/kusddrphy: phy has been simulated, remove from TODO 2017-07-07 09:03:54 +02:00
Florent Kermarrec b21a9d8e18 phy/kusddrphy: add phy reset (just to be sure primitives are correctly reseted, will be removed if not needed) 2017-07-07 09:02:58 +02:00
Florent Kermarrec fa3535f7c0 phy/kusddrphy: verify latencies with simulation 2017-07-06 19:21:38 +02:00
Florent Kermarrec abf028e0be global: reset_less optimizations 2017-07-01 11:18:05 +02:00
Florent Kermarrec 67df00bcac frontend/bist: use new reset_less attribute where possible 2017-06-29 11:20:08 +02:00
Florent Kermarrec c8713bfb48 litedram/frontend/bist: cleanup and add ticks counters to measure performance with hardware 2017-06-29 10:41:34 +02:00
Florent Kermarrec 6091c6de60 frontend: remove fifo, too complex to get working and too many corner cases (data stuck in pipeline, ...) 2017-06-28 12:30:59 +02:00
Florent Kermarrec 369e9308b9 frontend/fifo: simplify and only keep raw layout 2017-06-27 17:24:32 +02:00
Florent Kermarrec 883e97101a common: add id to ports 2017-06-27 15:06:12 +02:00
Florent Kermarrec 9ce2f67bb1 frontend: add dram fifo (untested) 2017-06-23 22:00:49 +02:00
Florent Kermarrec bab0150c87 README: consistency between projects 2017-06-22 16:57:14 +02:00
Florent Kermarrec 25d5674f33 test: remove test_bitslip (now in litex) 2017-04-24 18:49:20 +02:00
Florent Kermarrec 3fe29ddacc phy: BitSlip now integrated in LiteX 2017-04-19 09:58:27 +02:00
Florent Kermarrec 767b0144eb modules: add MT41J256M16 2017-03-14 20:59:02 +01:00
Florent Kermarrec ddb05b92b6 phy/kusddrphy: test implementation and fixes 2017-03-14 09:20:06 +01:00
Florent Kermarrec c04c288e66 phy/kusddrphy: fix OSERDESE3/ISERDESE3 data ports 2017-03-09 10:54:53 +01:00
Florent Kermarrec 98d9f1ffc0 test/test_bitslip: simplify BitSlipModel 2017-02-10 13:18:11 +01:00
Florent Kermarrec cd83448f8e README: update copyright 2017-02-10 13:08:09 +01:00
Florent Kermarrec 63434324e6 phy/kusddrphy: add TODO 2017-02-10 13:05:49 +01:00
Florent Kermarrec ac43e0118e phy/x7ddrphy: ease understanding of read latency loop range 2017-02-10 12:57:08 +01:00
Florent Kermarrec 478b8c1df3 phy/kusddrphy: integrate BitSlip module (in fabric) and instanciate ISERDESE3 2017-02-10 12:51:30 +01:00
Florent Kermarrec c94b1e7d0a phy: cleanup instances indentation 2017-02-10 10:06:31 +01:00
Florent Kermarrec 062177502b phy: add bitslip module (we need to implement it in logic for Kintex Ultrascale since not provided by ISERDESE3) 2017-02-10 08:59:13 +01:00
Florent Kermarrec 1430cb3d49 phy: add initial Kintex Ultrascale PHY (incomplete)
Input deserializer still missing, need to implement bitslip in logic and use new fifo interface.
Others primitives should be fine.
2017-02-09 13:25:45 +01:00
Florent Kermarrec 99550968e7 test: move BISTDriver to common and use it in test_bist_async 2017-01-17 15:18:10 +01:00
Florent Kermarrec 1bcab6303d setup.py: add test_suite 2017-01-17 15:17:21 +01:00
Florent Kermarrec d213a628f8 test/test_bist: use generator to corrupt memory (allow testing base address on checker/generator) 2017-01-17 14:35:34 +01:00
Florent Kermarrec 40168db0b4 test/test_bist: create BISTDriver to simplify test code 2017-01-17 14:31:24 +01:00
Florent Kermarrec 4f51524921 frontend/bist: rename err_count to errors 2017-01-17 14:30:23 +01:00
Florent Kermarrec c56f90e865 test/test_bist: simplify and test modules directly not through CSR 2017-01-17 14:14:50 +01:00
Florent Kermarrec e7fe539c73 frontend/bist: remove LiteDRAMBISTCheckerScope.
Checker should not be used to investigate errors but only to verify that is already validated still works. (ie we don't want to be able to understand what is going on, just to know if it's working or not). To understand what is going on we will look at signals with LiteScope and eventually trigger on err_count from checker.
2017-01-17 13:48:03 +01:00
Florent Kermarrec ad304c8997 test: convert to python unittests and some cleanup 2017-01-17 13:18:11 +01:00
enjoy-digital 53d11cf7e3 Merge pull request #5 from mithro/scope
Creating a utility module for easily scoping the LiteDRAMBISTChecker module.
2016-12-24 15:16:36 +01:00
Tim 'mithro' Ansell c142db3966 Creating a utility module for easily scoping the LiteDRAMBISTChecker module. 2016-12-19 17:49:24 +01:00
Florent Kermarrec aac61f346e test: start fixing bist_tb 2016-12-17 19:24:12 +01:00
Florent Kermarrec 0f151c5499 frontend/bist: small cleanup 2016-12-17 19:22:56 +01:00
Florent Kermarrec a613c49783 frontend/bist: cleanup the way we expose signals for debugging 2016-12-17 19:04:58 +01:00
enjoy-digital c090593e52 Merge pull request #3 from mithro/bist
Improve the BIST testbench and documentation
2016-12-17 18:33:38 +01:00
Tim 'mithro' Ansell e21b45b608 Merge remote-tracking branch 'upstream/master' into bist 2016-12-17 18:15:59 +01:00
Tim 'mithro' Ansell bc75d4f3d5 bist: Reworking as suggested by Florent. 2016-12-17 17:49:47 +01:00
Florent Kermarrec 5909e5d76e frontend/bist: refactor(simplify) LiteDRAMBISTChecker 2016-12-17 17:08:50 +01:00
Florent Kermarrec 381789c84d frontend/bist: refactor(simplify) LiteDRAMBISTGenerator, use start instead of shoot 2016-12-17 16:38:59 +01:00
Tim 'mithro' Ansell 70a333628b dma: Adding some documentation. 2016-12-17 14:09:50 +01:00
Tim 'mithro' Ansell fcc1d5059e bist: Improving documentation a bit. 2016-12-17 14:09:50 +01:00
Tim 'mithro' Ansell f1ad8991a4 bist: Working on improving the names of things. 2016-12-17 14:09:50 +01:00
Tim 'mithro' Ansell 8ff2f8779b bist: Adding "halt on error" functionality.
Also include ability to see address of error and expected verse actual
data values.

Extend the test bench to test this functionality.
2016-12-17 14:09:50 +01:00
Tim 'mithro' Ansell c0b8d1a714 bist: Adding some documentation.
(Plus small formatting cleanup.)
2016-12-17 14:09:50 +01:00
Tim 'mithro' Ansell da144f41d4 bist: Refactoring test bench.
Move a bunch of common code into common.py
2016-12-17 14:09:50 +01:00
Tim 'mithro' Ansell dc14a98bf4 bist: s/shoot/start/ 2016-12-17 14:09:50 +01:00
Tim 'mithro' Ansell 086b905e59 bist: Improve the basic test bench a little. 2016-12-17 14:09:50 +01:00